Standart IEEE 1450 (1999)

IEEE Standard Test InterfaceLanguage (STIL) for Digital TestVector DataIntroduction(This introduction is not part of IEEE Std 1450-1999, IEEE Standard Test Interface Language(STIL) for Digital TestVector Data.)Standard Test Interface Language(STIL) was initially developed by an ad-hoc consortium of test equipmentvendors, computer-aided engineering(CAE)and computer-aided design(CAD)vendors, and integrated circuit (Ic)manufacturers, to address the lack of a common solution for transferring digital test data from thegeneration environment to the test equipmentThe need for a common interchange format for large volumes of digital test data was identified as an overriding priority for the work; as such, the scope of the work was constrained to those aspects of the test environ-ment that contribute significantly to the volume issue, or are necessary to support the comprehension of thatdata. Binary representations of data were a key consideration in these efforts, resulting in a proposal to incorporate the compression of files as part of this standardLimiting the scope of any standards project is a difficult thing to do, especially for a room full of engineersHowever, issues that did not impact the scope as identified were dropped from consideration in this versionof the standard. Subclause lI covers, specifically, the capabilities that are not intended to be part of this firststandardEarly work in this consortium consisted of identifying the requirements necessary to address this problemand reviewing existing options and languages in the industry. All options proposed fell short of addressingthe requirements, and the consortium started to define a new language This work was executed with heavleverage from some existing languages and environments, and Stil owes much to the groundwork established by these other languagesParticipantsWhen the Stil Working Group approved this standard, it had the following membershipGreg maston Co-chairTony Taylor, Co-chairThe technical subgroup consisted of the following membersLarry moranMike purtellBrady HarveyGary murrayJim WardBrad HinckleChris nelsonGregg WilderDon organOther working group members were as followsSrinivas ajiarapuDon DenburgGary rainesPhil barchGivargis A. danialyTim WagnerAjit BhaveTom munnsTom williamsFred BernecheEric parkePeter WohlJoc Carbonefrank peytonStefan zschicgncrCopyrightC1999 IEEE All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions applyThe following members of the balloting committee voted on this standardPhil barchBrion KellerHira rangaKenneth m. butlerFadi maamariGordon robinsonJoe carboneA MastonJohn w. SheppardDonald denburgColin maunderWilliam R. simpsonDave dowdLarry L. moranny taylorGrady gileTom munnsJon udellGary ginnWayne NeedhamJim WardGary hancockChris nelsonGregg wildeBrady haJim O'ReillyPeter WohlMitsuaki ishikawaFrank peytonStefan ZschiegnerMike purtellThe Working Group thanks those companies that contributed concepts and ideas to this effort, in addition topeople and time. These contributions helped to define the language presented in this standard. In particular,the Working Group would like to thank: LTX Corporation, for providing information about the en visionenvironment; Motorola, Incorporated, for providing information about the Universal Test Interface CodeqUTIC); Test Systems Strategies, Incorporated, for providing information about the waveform GenerationLanguage (WGL); and Texas Instruments, Incorporated, for providing information about the Test Description Language (tdlyWhen the IEEE-Sa Standards board approved this standard on 18 March 1999, it had the followingmembersRichard J. Holleman. chairDonald n. heiman. vice chairJudith gorman secretarSatish K. AggarwalJames h. gurneyLouis-Francois PauDennis bodsonLowell G. JohnsonRonald c. petersenMark d. bowmanRobert J KennellyGerald h. petersonamesE.G."“AIKiJohn b. poseyGary r EngmanJoseph L. KoepfingerxGary s. robinsonHarold e. EpsteinL. Bruce mcclungAkio TojoJay Forster*Daleep c mohlaHans e. weinrichRuben d garzonRobert f munznerDonald w. zipse米率 Member emeritusAlso included is the following nonvoting IEEE-sa Standards board liaisonRobert e. heebnerJanet RutiglianoIEEE Standards Project EditorCopyright C 1999 IEEE. All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions applyContents1. Overview1.1 Scope.......1.2 Purpose2. Referennces3. Definitions, acronyms, and abbreviations43.2 Acronyms and abbreviations4. Structure of this standard5. STIL orientation and capabilities tutorial (informative)5.1 Hello Tester5.2 Basic ls245........135.3 STIL timing expressions/Spec"information5.4 Structural test(scan)……………………………………………25.5 Advanced scan265.6 IEEE Std 1149.1-1990 scan325.7 Multiple data elements per test cycle375.8 Pattern reuse/direct access test415.9 Event data/non-cyclized STIL information456.STILsyntaxdescription......................156.1 Case sensitivity…6.2 Whitespace非,.6.3 Reserved words6. 4 Reserved characters6.5 Comments·“··586.6 Token length6.7 Character strings·····.586.8 User-defined name characteristics6.9 Domain names·····*6.10 Signal and group name characteristics6. 1I Timing name constructs606. 12 Number charactcristics······*··6.13 Timing expressions and units( time expr)616.14 Signal expressions(sigref expr).....6.15 Waveform Char characteristics.6. 16 STIL name spaces and name resolution7. Statement structure and organization of sTIL information677. 1 Top-level statements and required ordering.....687.2 Optional top-level statements.707. 3 STIL filesCopyrightC1999 IEEE All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions apply8. STiL statement708.1 STIL708.2 STIL example709. Header block9.1 Header block syntax9.2 Headeaple10. Include10.1 Include statement syntax10.2 Include example10.3 File path resolution with absolute path notation710.4 File path resolution with relative path notationII. Userkeywords statement7311. 1 User Keywords statement syntax11. 2 USerKeywords example33乃12. User Functions statement12.1 UscrFunctions statement syntax12.2 User Functions example13.△ nn statement...7413. 1 Annotations statement syntax7413.2 Annotations example.7414. Signals block.......7414.1 Signals block syntax.14.2 Signals block example……15. SignalGroups block++““““““15. 1 SignalGroups block syntax15.2 Signalgroups block example···7815. 3 Default attribute values···“·15. 4 Translation of based data into waveform Char characters16. Pattern Exec block*+··········16. 1 Pattern Exec block syntax16.2 Pattern Exec block example8117. Pattern Burst block8117.1 Pattern Burst block syntax17.2 Pattern Burst block exampleCopyright C 1999 IEEE. All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions apply18. Timing block and Waveform Table block18.1 Timing and Waveform Table syntax……8418.2 Waveform event definitions18.3 Timing and WaveformTable example18.4 Rules for timed event ordering and waveform creation9018.5 Rules for waveform inheritance19. Spec and Selector blocks19. 1 Spec and Selector block syntax19.2 Spec and Selector block example96Scan Structures block9720. 1 Scan Structures block syntax…9820.2 Scan Structures block example9921. STIL Pattern data10021. 1 Cyclized data.……1,1021.2 Multiple-bit cyclized data10121.3 Non-cyclized data10221. 4 Scan data21.5 Pattern labels10322. STIL Pattern statements10322 1 Vector (V) statement22.2 Waveform Table(W)statement10422.3 Condition(C)statement10422.4 Call statement········+··:·:········*·“········:·:“·.10522.5 Macro statement10522.6 Loop statement22.7 MatchLoop statement10622. 8 Goto statement∴10722.9 Break Point statements··“··1022.10 IDDQTestPoint statement10722.11 Stop statement22.12 Scan Chain statementl0823. Pattern block….10823. 1 Pattern block syntax..............1083Pattern initialization......................................10923.3 Pattern examples10924. Procedures and macro Defs blocks24.1 Procedures block11024.2 Procedures example24.3 MacroDefs block24.4 Scan testing24.5 Procedure and Macro Data substitution112CopyrightC1999 IEEE All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions applyAnnex A(informative)Glossary116Annex b (informative) StiL data model····…···:·:·4·4·······“··117Annex C (informative)GNU GZIP reference22Annex D(informative) Binary STIL data formatAnnex E(informative) LS245 design description···127Annex F(informative) STIL FAQS and language design decisions129Copyright C 1999 IEEE. All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions applyIEEE Standard Test InterfaceLanguage(sTIL) for Digital TestVector data1. OverviewStandard Test Interface Language(STIL) is a standard language that provides an interface between digitaltest generation tools and test equipment. STIL may be directly generated as an output language of a test gen-eration tool, or it may be used as an intermediate format for subsequent processing Figure I shows StiLusage in a"pipe'"format. This is meant solely as a visual analogy to emphasize the high-volume/highthroughput requirements. It is not meant to represent physical structures or implementation requirementsSTIL is a representation of information needed to define digital test operations in manufacturing tests. STILs not intended to define how the tester implements that information while the purpose of stil is to passtest data into the test environment, the overall stil language is inherently more flexible than any particulartester. Constructs may be used in a Stil file that exceed the capability of a particular tester. In some circumstances, a translator for a particular type of test equipment may be capable of restructuring the data to support that capability on the tester; in other circumstances, separate tools may operate on that data to providethat restructuring. In all circumstances, it is desirable to provide the capability to check the data against theconstraints of a tester. This capability is referred to as Tester Rules Checking and is the domain of tools thatoperate on StiL data. As such, Tester Rules Checking operations are outside the scope of this standardFigure 2 shows how STiL fits into the data flow between computer-aided engineering(CAE)/Simulation andthe test environment. In this figure, STIL is shown as both the input and output of"STIL ManipulationTools. "STIL represents patterns as a series of cyclized waveforms that are executed sequentially. The wave-form representation can be as simple as a print-on-change set of events, or a complex set of parameterizedevents. Hence, tools may be required to manipulate the data according to the requirements of a particularclass of device, simulation, or tester. The output of that manipulation is still represented in StIlAnother issue presented in Figure 2 is the need for data from the tester to be transmitted back to theCAE/simulation environment for the purpose of correlating simulation data to tester data. Although this isrecognized as an important aspect of testing digital devices, it does not represent the data volume that thepatterns themselves do, and is not specifically supported in this version of the standardCopyright@ 1999 IEEE. All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions applylEEEstd1450-1999IEEE STANDARD TEST INTERFACE LANGUAGE (STILEditeesterAdjustperFormatterToolTest tranCAESTCAFTest tranFigure 1-A conduit for transporting data from cae to atEATPGruleSimulatorsInstructionsSTILSTILManipulationToolsTarget testerRulestranslatorInstructionscompilerDiagnosticⅤ ector&xrefs forSupportdebugmemorvSim->Pat)loadsDatalog fromFigure 2-STIL usage modelCopyright o 1999 IEEE. All rights reservedAuthorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on February 25, 2014 at 09: 38: 08 UTC from IEEE Xplore. Restrictions apply