ar0130detasheet

百万像素摄像头AR0130数据手册 引脚分布 设计Aptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorTable of contentsBlack level correction28Row-wise noise correction28Column CorrectionColumn Correction Triggering.·.·····Defective pixel correction30Test patternsColor fieldVertical color bars30Walking lTwo-Wire Serial register InterfaceProtocol51Start Condition31Stop Condition.................,,,31Data Transfer31Slave Address/Data Direction ByteMessage byte32Acknowledge bit........32No-Acknowledge bitTypical Sequence...........Single read from random location····Single read from Current locationSequential READ, Start from Random Location.............Sequential READ, Start from Current Location34Single Write to Random Location34Sequential WrITE, Start at Random LocationSpectral characteristicsPackage dimensions·...37Electrical specifications垂垂垂Two-Wire Serial Register Interface38I/0 Timing.……………DC Electrical characteristics41HiSPi Electrical Specifications44Power-On Reset and Standby Timing46Power-UP See46Power-Down Sequence...48Revision history4327/ Source660323313Aptina reserves the right to change products or specificatieARO130 Ds-Rev B Pub. s/llENh时nAptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorList of figuresList of FiguresFigureBlock diagramFigure 2: Typical Configuration: Serial Four-Lane HiSPi InterfaceFigure 3: Typical Configuration: Parallel Pixel Data InterfaceFigure 4: 48-Pin ilCC Pinout Diagram67801Figure 5: Pixel Array DescriptionFigure 6: Pixel Color Pattern Detail (Top Right Corner)Figure 7: Imaging a SceneFigure 8: Spatial Illustration of Image Readout13Figure 9: Default Pixel Output timing14Figure 10: LV Format Options14Figure 11: HiSPi Transmitter and Receiver Interface Block Diagram.15Figure 12: Timing Diagram15Figure 13: Line Timing and FRAME_ VALID/LINE- VALID Signals16Figure 14: PLL-Generated Master Clock PLL SetupFigure 15: Six Pixels in Normal and Column Mirror Readout modesFigure 16: Six Rows in normal and row mirror Readout modesFigure 17: Frame Format with Embedded Data Lines EnabledFigure 18: Format of Embedded Statistics Output within a frame2Figure 19: Single READ from Random LocationFigure 20: Single READ from Current LocationFigure 21: Sequential READ, Start from Random LocationFigure 22: Sequential READ, Start from Current Location34Figure 23: Single WRITE to Random Location34Figure 24: Sequential WRITE, Start at Random locationFigure 25: Estimated Quantum Efficiency-Monochrome SensorFigure 26: Estimated Quantum Efficiency-Color SensorFigure 27: 48 iL.CC Package Outline drawing.·.·垂37Figure 28: Two-Wire Serial Bus Timing Parameters.38Figure 29: 1/0 Timing DiagramFigure 30: Differential Output voltage for Clock or Data pairsFigure 31: Eye Diagram for Clock and Data SignalsFigure 32: Skew Within the PHY and Output Channels4556Figure 33: Power UpFigure 34: Power Down4327/ Source660323313Aptina reserves the right to change products or specificatieARO130 Ds-Rev B Pub. s/llENh时nAptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorList of tablesList of TablesTable 1Key ParametersTable 2.Available part Numbers.………Table 3Pad descriptions·····Table 4Frame Time(Example based on 1280 x 960, 45 Frames Per Second)..16Table 5: Frame Time: Long integration TimeTable 6: Real-Time Context-Switchable registersn18Table 7Test Pattern modesTable 8: Two-Wire serial Bus characteristicsTable 9I/O Timing CharacteristicsTable 10: DC electrical characteristicsTable 11: Absolute Maximum Ratings41Table 12: Operating Current Consumption in Parallel Output····:···.·:··;········42Table 13: Operating Currents in HiSPi Output42Table 14: Standby Current Consumption鲁香·P43Table 15: Input Voltage and CurrentTable 16: Input Voltage and currentTable 17: rise and Fall Times44Table 18: Channel, phY, and Intra-PHY Skew45Table 19: Power-Up Sequence.............47Table 20: Power-Down Sequence484327/ Source660323313Aptina reserves the right to change products or specificatieARO130 Ds-Rev B Pub. s/llENh时nAptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorGeneral DescriptionGeneral DescriptionThe Aptina aro130 can be operated in its default mode or programmed for framesize, exposure, gain, and other parameters. The default mode output is a 960p-resolutionimage at 45 frames per second (fps). It outputs 12-bit raw data, using either the parallelor serial (HisPi)output ports. The device may be operated in video(master)mode or insingle frame trigger modeFRAME VALID and line VALID signals are output on dedicated pins along with asynchronized pixel clock in parallel modeThe aro130 includes additional features to allow application-specific tuningwindowing and offset, adjustable auto-exposure control, auto black level correction, andon-board temperature sensor Optional register information and histogram statisticinformation can be embedded in first and last 2 lines of the image frameFunctional overviewThe aro130 is a progressive-scan sensor that generates a stream of pixel data at aconstant frame rate. It uses an on-chip, phase-locked loop(Pll) that can be optionallyenabled to generate all internal clocks from a single master input clock running between6 and 50 MHz The maximum output pixel rate is 74.25 Mp/s, corresponding to a clockrate of 74.25 MHz. Figure I shows a block diagram of the sensorigure 1: Block DiagramExternalOTPMMemoryPLLActive pixel sensorClock(APS)Timing and ControlowerAuto ExposureSequencerand Stats EngineSerialOutputPixel data pathParallelAnalog Processing and(Signal Processing)OutputA/D ConversionTWo-WireSeriaControl registersInterfaceUser interaction with the sensor is through the two-wire serial bus which communicates with the array control, analog signal chain, and digital signal chain. The core of thesensor is a 1.2 Mp Active- Pixel Sensor array. The timing and control circuitry sequencesthrough the rows of the array, resetting and then reading each row in turn. In the timeinterval between resetting a row and reading that row, the pixels in the row integrateincident light. The exposure is controlled by varying the time interval between reset andreadout. Once a row has been read, the data from the columns is sequenced through ananalog signal chain (providing offset correction and gain), and then through an analogto-digital converter (ADC). The output from the adC is a 12-bit value for each pixel inthe array. The adc output passes through a digital processing signal chain (which4327/ Source660323313Aptina reserves the right to change products or specificatieARO130 Ds-Rev B Pub. s/llENh时nAptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorFunctional overviewprovides further data path corrections and applies digital gain). the pixel data areoutput at a rate of up to 74.25 Mp/, in parallel to frame and line synchronizationSignalsFigure 2: Typical Configuration: Serial Four-Lane HiSPi InterfaceDigital DigitalCoreHiSPiPLL Analog Analoower- power- pVDD O VDD9 VDD PLL VAA VAA PIXCmSO NMaster clockEXTCLK(6-50MHz)SLVSI NSLVS2 PSAuLSDATASLVS3 PcontrollerFromcontrollerTRIGGERSLVS3 NLVSCSTANDBYSLVSC NRESET BAIReserveDGNDAGNDVDD OVDDVDD SLVS VDD PLLVAVAA PIXDigitalroundNotes: 1. All power supplies must be adequately decoupled2. Aptina recommends a resistor value of 1. ko2, but a greater value may be used for slower two-wireeed3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times4. The parallel interface output pads can be left unconnected if the serial output interface is used5. Aptina recommends that o luF and 10u F decoupling capacitors for each power supply aremounted as close as possible to the pad. Actual values and results may vary depending on layoutand design considerations. Check the aRo130 demo headboard schematics for circuit recommenratio6. Aptina recommends that analog power planes are placed in a manner such that coupling with thedigital power planes is mi7. l0 signals voltage must be configured to match VDD l0 voltage to minimize any leakage currents8. HiSPi interface is available only on Bare Die package option4327/ Source660323313Aptina reserves the right to change products or specificatieARO130 Ds-Rev B Pub. s/llENh时nAptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorFunctional overviewFigure 3: Typical Configuration: Parallel Pixel Data InterfaceDigital Digio corePLIL Analog Analogpower- powerlpower- power powerVDD PLL VAA VAA PIXMaster clockEXTCLK6-50MHz)ou[110PIXCLKLINE VALIDSDATAcontrollerTRIGGERController-o oE BarSTANDBY+o RESEt BARDGNDAgNDVDD IOVDD PLLVAA PIXDigitalAnaloroundgrolnotesAll power supplies must be adequately decoupled2. Aptina recommends a resistor value of 1.5ks2, but a greater value may be used for slower two-Wire3. This pull-up resistor is not required if the controller drives a valid logic level on ScLK at all times.4. The serial interface output pads andleft unconnected if the parallel output intface is used for lowest standby leakage current aptina recommends that vdd slvs is tied to 1.8Vstead of floati5. Aptina recommends that 0. 1uF and 10uF decoupling capacitors for each power supply aremounted as close as possible to the pad. Actual values and results may vary depending on layoutand design considerations. Check the aRo130 demo headboard schematics for circuit recomme6. Aptina recommends that analog power planes are placed in a manner such that coupling with thedigital power planes is minimized7. l0 signals voltage must be configured to match VDD lO voltage to minimize any leakage currents4327/ Source660323313ARO130 Ds-Rev B Pub. s/llENAptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorFunctional overviewTable 3: Pad DescriptionsNameTypeDescriptionSLVSO_N Output HiSPi serial data, lane 0, differential NSLVSO PHiSPi serial data, lane 0, differential PSLVS1 N Output HiSPiserial data, lane 1, differential NSLVS1_P Output HiSPi serial data, lane 1, differential PSTANDBY Input Standby-mode enable pin(active HIGH).VDD PLLPowerPLL power.SLVSC NOutputHiSPi serial ddr clock differential nSLVSC P Output HiSPi serial DDR clock differential PSLVS2 NOutputHiSPi serial data lane 2. differential NSLVS2 POutputHiSPi serial data, lane 2, differential P.VAAPowerAnaleog pEXTCLKInputExternal input clock.VDD SLVSPowerHiSPI power.SLVS3_N Output HiSPi erial data, lane 3, differential N.SLVS3 POutputHiSPi serial data. lane 3, differential pDGNDPowerDigital groundVDDPowerDigital powerAGNDPowerAnalog groundInput Two-Wire Serial address select.InputTwo-Wire Serial clock inputSDATAyOTwo-Wire Serial data I/OVAA PIXPixel powerLINE_VALID Output Asserted when DOUT line data is validFRAME_VALID Output Asserted when DOuT frame data is valid.PIXCLKatpuPixel clock out. douT is valid on rising edge of this clock.VDD OPowerl 0 supply power.DoUT8Output Parallel pixel data outputDOUT9OutputParallel pixel data outputDOUT10 Output Parallel pixel data outputDOUT11Output Parallel pixel data output(MSB)ReservedInputConnect to DGND.DOUT4Output Parallel pixel data outputDOUT5OutputParalleldata outputDOUT6Output Parallel pixel data outputOutParallel pixel data outputTRIGGERInputExposure synchronization inputOE BAR InpOutput enable(active LOWDOUTOOutput Parallel pixel data output(LSB)DOUT1Output Parallel pixel dataOUT2Output Parallel pixel data outDOUT3Output Parallel pixel data outputRESET BARInputAsynchronous reset (active LOW). All settings are restored to factory default.FLASHOutput Flash control outputDo not connect4327/ Source660323313Aptina reserves the right to change products or specificatieARO130 Ds-Rev B Pub. s/llENh时nAptina Confidential and ProprietaryPreliminaryAPtinaARO130: 1/3-Inch CMOS Digital Image SensorFunctional overviewFigure 448-Pin iLCC Pinout DiagramNODou8匚841 NCDour 990匚VDOUT 10 F1039 AgNDDOUT 11VAAP|ⅨXⅩCLK厂13DD匚35F AGNDK匚15RESET BAR二17NOVDD|O□18192021222324252527282930e224327/ Source66032331310Aptina reserves the right to change products or specificatieARO130 Ds-Rev B Pub. s/llENh时n