cpri_useguide

cpri协议；R XILINXALL PROGRAMMABLEnChapter 5: Design Flow StepsCustomizing and generating the core........................ 138Constraining the Coren,,..151Simulation....,,,,,,,,,.,,,,,.,,,n,,156Synthesis and Implementation156Chapter 6: Example designChapter 7: Test BenchAppendix A: Verification, Compliance, and InteroperabilitySimulation,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,。,,。,,,,,,,,,,,,,,,,,,,,,,,165Hardware TestingAppendix B: Migrating and UpgradingMigrating to the vivado Design Suite166upgrading in the vivado Design Suite,.166Appendix C: DebuggingFindingHelponXilinx.com173Vivado Design Suite Debug Feature,174Hardware Debug...,.......175AX14-Lite Interface Debug......,,..176Appendix D: Additional Resources and Legal NoticesXilinx resources177References177Revision History178Please Read: Important Legal Notices,,,。,。,,。,,,,,,,。,。,180CPRI V8. 7Send feedbackPG056Apri5,2017www.xilinx.comXL|NⅩIP FactsALL PROGRAMMABLEIntroductionLogICORE IP FactsCore specificsThe logicoreTm ip common public radioInterface(CPRIM)core is a high -performance,Zynq ( R UltraScale+ M MPSocUltraScale+low-cost flexible solution for implementation ofSupporteUltraScaletmthe Cpri interface it uses state-of-the-artDevice Family(l)Zyng- 7000 All Programmable SoC(2)7 Seriestransceivers to implement the Physical Layer. aSee speed grade Supportcompact and customizable data Link Layer isGeneric data, status, configuration andimplemented in the fpga logicSupported usermanagement interfacesInterfacesAXI4-Lite management interfaceFeaturesResourcesPerformance and resource utilization web pageProvided with coreUltra Scale architecture device designsDesign FilesEncrypted register transfer level(RTL)operate at line rates of 614.4, 1, 228.8,Example DesignVHDL2,457.6,3,072,4,915.2,6,144,8,110.08,9,8304,10,137.6,12,16512,andTest benchVHDL24, 330.24 Mb/s using GTHE3, GTYE3, GTHE4 Constraints FileXilinx Design Constraints(XDC)or gtye4 transceiversSimulationModels∨HDL, VerilogOptional RS-FEC supported using GTYE3Supportedand gtye4 transceivers at 24,330.24N/AS/W Drivers12,16512,10,137.6and8,110.08Mb/ s lineTested Design Flows(4)ratesDesign EntryVivado@ Design SuiteZynq-7000, VirtexR-7, and KinteX(R-7SimulationFor supported simulators see thedevice designs operate at line rates ofXilinx Design Tools: Release Notes Guide61441,2288,2,457.6,3072,491526144 SynthesisVivado Synthesis9,830.4, and 10,137.6 Mb/s using GTXE2SupportGTHE transceiversProvided by Xilinx at the Xilinx Support web pageArtixR-7 devices designs operate at lineNotes:rates of6144,1,228.862,457.6,3,072,1. For a complete list of supported devices, see the Vivado IP4, 915.2, and 6,144 Mb/s using gtpe2catalog2. Excludes the Zynq-7000 010 and 020 devicestransceivers3. Excludes the artix-7 100T device in CSG324 and FTG256packagesUTRA-FDD in-phase and quadrature-phase4. For the supported version of the tool, see thedata(I/Q)module supporting 1 to 48Xilinx Design Tools: Release Notes GuideAntenna-Carriers per coreAutomatic speed negotiationSupports both Fast(Ethernet)and SlowHigh-Level Data Link Control(HDLC)Control and management(C&M) channelsper CPRI Specification v7.0 [Ref 1CPRI V8. 7Send fePG056Apri5,2017www.xilinx.comProduct SpecificationⅩL|NXALL PROGRAMMABLEChapter 1OverⅰeWCPRITM is a standard for communication between a Radio Equipment Controller(REC)orBase Station and one or more Radio Equipment(re)units in a cellular network. By defininga publicly available specification for the key internal interface between these units, anindependent technology evolution is fostered for cellular equipment products. Figure 1-1shows the position of the interface within a cellular system. the CPri v8.7 core has beendesigned to the CPr/ Specification v7.0 [Ref 1EquipmentEquipmentRadiController(REEquipment(REC)CPRICPRICPRICPRIMasterSlaveMasterSlaveBackplane, Cable or FiberFigure 1-1: Location of CPRI in a Cellular SystemThe CPRi core implements Layer 1 and Layer 2 of the CPRI specification in UltraScale TMdevices, Zyng -7000 All Programmable SoCs, and 7 series devicesFeature SummaryDesigned to CPRI Specification v7.0 [Ref 1Can be configured as a master or slave at generation time. Master core can be switchedto operate as a slave through a configuration portSuitable for use in both radio equipment Controllers(ReCs)and radio equipment(re),including multi-hop systemsEasy-to-use interface for in-phase (I)and quadrature-phase( Q)data andsynchronization together with optional modules for UmtS terrestrial radio accessfrequency division duplexing(UTRA-FDD)and Evolved UMTS Terrestrial Radio access(E-UTRA)data mappings interfaceSupports both ethernet and HDLC Control and Management channelsCPRI V8. 7Send feedbackPG056Apri5,2017www.xilinx.comR XILINXChapter 1: OverviewALL PROGRAMMABLESupports vendor-specific data transport including support for the passing of controlAxC information in global system for mobile communications(GSM)systemsIncludes the necessary clocking and transceiver logic to enable easy integration intoyour designSynthesizable example design and simple demonstration test bench providedDelay measurement capability meets CPri Requirement 21 per CPR/ Specification v7.0Ref 1Optional reed-Solomon Forward Error Correction(RS-FEC)supported at8,110.08Mb/s,10,137.6Mb/S,12,165.12Mb/sand24,330.24Mb/ s ine rates.ApplicationsThe goal of the CPri interface is to use one physical connection for the radio data(l/Q dataradio unit management(for example, Automatic Gain Control, alarmsand synchronization(clock frequency control, frame synchronization). Table 1-1 shows the data rates supportedby each Xilinx device. Data is transferred over a single serial link. This link is defined to beelectrically compliant with existing high-speed serial link standards such as the gigabitEthernet and 10 Gigabit eXtended Attachment Unit Interface(XAUI)standardsTable 1-1: Supported Data RatesFrequency in Mb/sFamily6144)1228245753072049152614081089830.4101376121512324Virtex-7-1 speed grade YesYesYesYesYesesNoNoNoNo2 speed grade YeesYesesNYNoNo-3 speed grade YesYesYesYEYesYesYesYYYesNoKintexo-7 and Zyng-7000ed gradeRYesYees-2 speed gradeYYesYeYesYesYesNoYes(2) NoNo-3 speed gradeYesYesYeesYesYesYesNoYes(2)Yes(2) Yes(2)No1 speed grade YesYesYes Yes NoNoNo No No NorNo2/-3 speedYesYesYesYegradeUltraScaletm and ultraScale+t1 speed grade YesYesYes YesYesYesYesYes Yes YesYes(4)2/3 speedYesYesYesYesYesYesYeYesYesgradeCPRI V8. 7Send feedbackPG056Apri5,2017www.xilinx.comR XILINXChapter 1: Overviewable 1-1: Supported Data Rates Cont'd)Frequency in Mb/sFamily6144(1)1,2282,457.63072.04,915.2614408,11089830410137.612,165122430.24Zyng ultraScale m+ MPSoc1 peed grade YesYesYesYesYesYesYesYesYesYes Yes(4)-2/-3 speedYesYeYeYesYesYesYesYesYesYes(5)gradeNot1. The 614. 4 Mb/s line rate is not supported when the Ori option is selected2. Not supported on non Pb-free flip-chip BGA(FFG) packages3. Not supported on wire-bond packages4. Only supported on UltraScale+ devices using GTYE4 transceivers5. Only supported on UltraScale devices using GTYE3 transceivers and on UltraScale+ devices using GTYE4transceiversSystem RequirementsFor a list of System requirements see the Xilinx design tools: Release Notes guideRecommended Design ExperienceAlthough the CPRi core is a fully-verified solution, the challenge associated withimplementing a complete design varies depending on the configuration and functionalityof the application. For best results, previous experience building high performance,pipelined fpga designs using Xilinx implementation software and the Xdc file isrecommendedContact your local Xilinx sales representative for a closer review and estimation for yourspecific requirementsLicensing and Ordering InformationLicense checkersIf the IP requires a license key, the key must be verified. The vivado b design tools haveseveral license check points for gating licensed IP through the flow. If the license checksucceeds, the ip can continue generation Otherwise, generation halts with error. Licensecheckpoints are enforced by the following tools: Vivado design tools: Vivado synthesisVivado implementation, write_bitstream(Tcl Command)CPRI V8. 7Send feedback7PG056Apri5,2017www.xilinx.comR XILINXChapter 1: OverviewRAMMABLEIMPORTANT: The /P license level is ignored at checkpoints. The test confirms a valid license exists. Itdoes not check ip license levelIMPORTANT: To use the optional 32G Fiber Channel (32GFC) RS-FEC sub-core, contact your local Xilinxsales representative to obtain your free licenseLicense TypeThis Xilinx LogiCo RETM IP module is provided under the terms of the Xilinx Core LicenseAgreement For full access to all core functionalities in simulation and in hardware, youmust purchase a license for the core. Contact your local Xilinx sales representative forinformation about pricing and availability of Xilinx LogICORE IPFor more information, visit the CPri product pageInformation about this and other Xilinx logiCoRE IP modules is available at the XilinxIntellectual Property page For information on pricing and availability of other xilinxLogicore IP modules and tools contact your local xilinx sales representativeCPRI V8. 7Send feedbackPG056Apri5,2017www.xilinx.comⅩL|NXALL PROGRAMMABLEIMChapter 2Product SpecificationThe CPRITM core implements Layer 1 and Layer 2 of the CPRi specification in UltraScaleTmarchitecture-based, Zyng-7000 and 7 series devices. The CPri core provides the followingclient-side interfacesI/Q Interface: Consists of a stream of radio data(l/Q samples) that is synchronized tothe Universal Mobile Telecommunications System(UMTS)radio frame pulseSynchronization Interface: Provides the means for the client logic to synchronize tothe network time by transmitting the UMTS radio frame pulse and clock frequencyHigh-Level Data Link Control (HDLC)Interface: Transports management informationbetween master and slave. the hdlc interface is serialized and synchronousEthernet Interface: When configured to support speeds of up to 3,072 Mb/s, theEthernet interface is presented as a Media Independent Interface(MIl); this allows a100 Mb Ethernet Media Access Controller (MAC)to be attached to the core to provide ahigh-speed channel for management information When speeds over 4,915.2 Mb/s aresupported, a Gigabit Media Independent Interface(GMIl)option is available. Thisallows a 1 gb ethernet mac to be attached to the core. the core includes an ethernetframe buffer in both transmit and receive directions the frame buffers are derivedfrom the FIFo Generator and block Memory Generator IP coresVendor-Specific Data Interface: Provides client logic access to the vendor-specificsub-channels in the cpri streamManagement Interface: Provides control and status registers that allow managemetof the entire design from a supervisory processorThe architecture of the core is shown in Figure 2-1. In addition to the interfaces describedpreviously, the core contains these blocksStatus/Alarm Block: reflects the internal state of the core and the state of the linkStart-up Sequencer: Performs line-rate negotiation and Control and managementC&M) parameter negotiation at link start-up. this block continuously monitors thestate of the link and sends the status to the alarm blockUMTS Terrestrial Radio Access- Frequency Division Duplexing (UTRA FDD)I/QModule: A pluggable I/Q module to support multiplexing and demultiplexing of I/Qsamples in UTRA FDD systems(shown in Figure 2-1)CPRI V8. 7Send feedbackPG056Apri5,2017www.xilinx.comR XILINXChapter 2: Product SpecificationALL PROGRAMMABLEEvolved UMTS Terrestrial Radio Access(E-UTRA)I/Q Module: A pluggable I/Qmodule to support multiplexing and demultiplexing of I/Q samples in E-UTRA systems(not shown in Figure 2-1)Legacy raw I/Q Module: a pluggable I/Q Module for backward compatibility with theraw interfacing timing for CPRI cores(not shown in Figure 2-1)UTRA FDD1/Q Modulepri coreTⅩPatIControlTⅩ/ q data#1TⅩ/ o data#2I w/Q dataTⅩTXIQ data #48SpecificFIFOEthernFIFOGTHDLCtransceiverStartupRX I/Q data #1SequencingL1 SynchdRXCDCRX I/Q data#2-l/Q dataRX IQ data#48ManagementRX PathControFigure 2-1: CPRI Top-Level Block DiagramAs well as the low-level I/ Q Interface of the core, there are additional i/Q modules that shipwith the core to implement mapping and unmapping of I/Q samples, in accordance with theUniversal Mobile telecommunications System(UMTS) Terrestrial Radio Access-FrequencyDivision duplexing(Utra-FDD)and the evolved UMtS Terrestrial radio access(E-UTRAmappings in the CPR/ Specification V7.0 [Ref 1CPRI V8. 7Send feedback10PG056Apri5,2017www.xilinx.com