Spartan-6 FPGA 数据手册

Spartan-6 FPGA Data Sheet 学fpga必不可少的东西R XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsTable 2: Recommended Operating Conditions(1)(Cont'd)MemoSymbolDescriptionTemperature Speed ControllerRangeGradeBlock(2)MinTypMax UnitsPerformanceMaximum current through pin using PCI Commercial-4, -3, -2N/A10VO standard when forward biasing themA8)clamp diodeIndustrial3.-2N∥/A10mABattery voltage relative to GND, T=0C Commercial-4, -3,-2N/Ato +85C1L(XC6sLX75, XC6SLX75T, XC6SLX100XC6SLX100T. XC6SLX150 andXC6SLX150T only3.6Battery voltage relative to GND,Industrial-3, -2, -1LN/ATi=-40C to +100C (XC6SLX75,C6SLX75T. XC6SLX100XC6SLX100T. XC6SLX150 andXC6SLX150T onlyNote1. All voltages are relative to ground3. Recommended maximum voltage droop for VccAux is 10 mV/ms4. Configuration data is retained even if Vcco drops to o5. Includes Vcco of 1.2V,1.5V,1.8V, 2.5V, and 3.3V6. For PCI systems, the transmitter and receiver should have common supplies for Vcco7. Devices with a -1L speed grade do not support Xilinx PCI IP.8. Do not exceed a total of 100 ma per bank9. VBATT is required to maintain the battery backed RAM(BBR) AES key when V GND. However, VBATT can be unconnecla BATt can beis not applied. Once VccAUx is applied, VEunconnected. When BBR is not used, Xilinx recommends connecting to VCCAUXTable 3: eFUSE Programming Conditions(1)Symb。olDescriptionMin Typ Max UnitsVes 2) External voltage supply323.334fs VFs supply current40 mAVccAuX Auxiliary supply voltage relative to GND3233345VRFUSE 3)EXternal resistor from RFUSE pin to GND1129114011519ccINT Internal supply voltage relative to GND1.141.21.26Vt Temperature range15Notes1. These specifications apply during programming of the eFUSE AES key Programming is only supported through JTAG. The AES key is only supportedin the following devices: XC6SLX75, XC6SLX75 T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX 150T2. When programming eFUSE, Ves must be less than or equal to Vccaux When not programming or when eFUsE is not used, Xilinx recommendsconnecting VEs to GND. However \ ps can oe between GND and3. An RFUSE resistor is required when programming the eFUSE AES key. When not programming or when eFUSE is not used, Xilinx recommendsconnecting the RUSE pin to VccauX or GND. However, RFUSE can be unconnected.DS162(1.9) August23,2010www.xilinx.comAdvance Product SpecificationR XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsTable 4: DC Characteristics Over Recommended Operating ConditionsSymbolDescriptionMin Typ Max UrVDRInT Data retention VCcINT Voltage(below which configuration data might be lost0.8VDRAUX Data retention VccAux voltage(below which configuration data might be lost)2.0REFVREF leakage current per pin-1010AInput or output leakage current per pin (sample-tested10AAll pins except PROGRAM_B, DONE, and20」Aeakage current on pins during hotJTAG pins when HSWaPen= 1socketing with FPGA unpoweredPROGRAM_B, DONE, and JTAG pins, or otherS TRPUHApins when HSWAPEN=oNDie input capacitance at the pad10FPad pull-up(when selected)@ vin=OV, Vcco=3.3V or VccAUx =3.3V200500APad pull-up(when selected)@ Vin=ov, Vcco=2.5V or VCcAUX =2.5v120350APad pull-up(when selected)@ VIN=OV,VCco =1.8V200APad pull-up(when selected)@ VIN=OV,Vcco=1.5V40150μAPad pull-up(when selected)@ VIN=OV,Vcco=1.2V12100pAPad pull-down(when selected)@ VIN=Vcco: VCcAUX =3.3V200550APad pull-down(when selected)@ VIN=VcCO: VCCAUX =2.5V140400μABATTBattery supply current150nARDT(2) Resistance of optional input differential termination circuit, VcCAUx-33V100Thevenin equivalent resistance of programmable input termination23(UNTUNED_ SPLIT_25(4) Thevenin equivalent resistance of programmable input terminationRIN_TERM(UNTUNED_SPLIT_50395072Thevenin equivalent resistance of programmable input termination75109(UNTUNED_SPLIT_75)Notes1. Maximum value specified for worst case process at 25C. XC6sLX75 XC6sLX75T, XC6sLX100, XC6sLX100T, XC6sLX150 and XC6SLX 150T2. Refer to IBIS models for RDt variation and for values at VCCAUx=2.5V3. Vcco2 is not required for data retention. The minimum Vcco2 for power-on reset and contiguration is 1.65V4. Termination resistance to a Vcco/2 levelDS162(1.9) August23,2010www.xilinx.comAdvance Product Specification4R XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsQuiescent CurrentTypical values for quiescent supply current are specified at nominal voltage, 25C junction temperatures(Ti Quiescentsupply current is specified by speed grade for Spartan-6 devices. Xilinx recommends analyzing static power consumptionusingtheXpowErtmEstimator(xpe)tool(downloadathttp:/www.xilinx.com/power)forconditionsotherthanthosespecified in Table 5Table 5: Typical Quiescent Supply currentSpeed GradeSymboDescriptionDeviceUnits432C1LcciNtQ Quiescent VCCINT supply currentXC6SLX4n/A4.04.02.4XCOSLX9n/A4.04.02.4XC6SLX16N/AAAA60604.0XC6SLX25N/A11.011.06.6mAXCOSLX25T11.011.011.0N/AAXC6SLX45N/A1501509.0AXC6SLX45T15015.0150N/AmAXCOSLX75N/A29.029017.4XC6SLX75T29029029.0N/AmmXCOSLX100AAAN/A36.036021.6XCOSLX1O0T36.036.036.0N/AmAXC6SLX150n/A51.051.031.0mAXCOSLX150T51.051.051.0N/AmAQuiescent Vcco supply currentXC6sL×4N/A1.01.01.0XC6SLX9N/A1.01.01.0AXCOSLX16N/A2.02.02.0mAXC6SLX25N/A2.02.02.0mAXC6SLX25T2.02.02.0N/AmAXC6SLX45N/A303.03.0mAXC6SLX45T3.0303.0NAXCOSLX75N/A4.04.04.0mXC6SLX75T4.04.04.0NAmAXCOSLX100n/A50505.0DAXCOSLX1O0T5.05050N/AmAXCOSLX150N/A7.07.07.0mAXCOSLX150T7.07.07.0N/AmADS162(1.9) August23,2010www.xilinx.comAdvance Product Specification5R XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsTable 5: Typical Quiescent Supply Current (Cont'd)Speed GradeSyimboDescriptionDeviceUnits321LccauxQ Quiescent VCcAuX supply currentXC6SLX4N/A2.52.52.5AXC6SLX9N/A2.52.5mAXC6SLX16N/A303.03.0XC6SLX25N/A4.04.04.0XCOSLX25T4.04.04.0N/ADAXC6SLX45N/A50505.0mAXC6SLX45T505050N/AAXC6SLX75N/A7.07.07.0mAXCOSLX75T7.07.07.0N/AXCOSLX100N/A909.09.0mAXCOSLX1O0T9.0909.0N/AmAXCOSLX150N/A12.012.012.0mAXC6sL×150T12.0120120N/AANotes:1. TyIpical values are specified at nominal voltage, 25C junction temperatures(T]. Industrial grade devices have the same typical values ascommercial ( C grade devices at 25 C, but higher values at 100C. Use the XPE tool to calculate 100 C values2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors. all vO pins are 3-state and floating3. If differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator(XPE)or XPOWERAnalyzer(×PA) toolsTable 6: Power Supply Ramp TimeSymbolDescriptionSpeed GradeRamp TimeUnitsCCINTRInternal supply voltage ramp time4,-3,-20.20to50.0ms-IL0.20to40.0msCCO2Output drivers bank 2 supply voltage ramp time0.20to50.0nsmCCAUXRAuxiliary supply voltage ramp timeAll0.20to50.0msNotes.1. The minimum Vccoa for power-on reset and configuration is 1.65V2. Spartan-6 FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumeddepends on the power-on ramp rate of the power supply. Use the XPOWER Estimator (XPE)or XPOWER Analyzer (XPA)tools to estimate currentdrain on these supplies. Spartan-6 devices do not have a required power-on sequence.DS162(1.9) August23,2010www.xilinx.comAdvance Product Specification6R XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsSelectIoTM Interface DC Input and output levelsTable 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standardsv1o Standardcco for Drivers(1)VREF for InputsV MinV, NomV MaxV MinV NomV MaxLVTTL3.03.33.45LVCMOS333.03.33.45LVCMOS252.32.52.7LVCMOS181.65181.95LVCMOS18 JEDEC1.651.81.95LVCMOS151.41.51.6LVCMOS15 JEDEC1.4151.6LVCMOS121.11.213VREF is not used for these I/O standardsLVCMOS12 JEDEC1.11.2PC333(2)303.33.45PC|663(2)303.33.4512C2.73.03.45SMBUS2.73.03.45303.33.45MOBILE DDR1819HSTL I1.41.51.60.680.750.9HSTL I1.4151.60.680.750.9HSTLⅢ1.4151.60.9HSTL181.71.8190.80.9HsTL‖181.80.9HsTL川181.819SSTL303.33.451.31.51.7SsTL3‖303.33.451.31.5sstL2.32.52.71.131.251.38ssT2‖l22.52.71.131.25138SSTL18181.908330.90.969ssTL18‖l1.81.90.8330.90.969ssT15‖l1.4251.515750.690.7581Notes1. Vcco range required when using I/0 standard for an output. Also required for PCI33_3, LVCMOS18_JEDEC, LVCMOS15-JEDEC, andLVCMOS12-JEDEC inputs, and for LVCMOS25 inputs when VCcAUx=3. 3V2. For PCI systems, the transmitter and receiver should have common supplies for ccoDS162(1.9) August23,2010www.xilinx.comAdvance Product Specification&A XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsTable 8: Recommended Operating Conditions for User lOs Using Differential Signal StandardsVcco for Driversyo StandardV MinV NomV MaxLVDS 333.03.3345LVDS 252.252.52.75BLVDS 252.252.52.75MINI LVDS 333.03.33.45MINI LVDS 252.2522.75LVPECL 33(1)N/A-Inputs OnlyLVPECL 25N/A-Inputs OnlyRSDS 333.03.33.45RSDS 252.252.52.75TMDS 33(1)3.143.33.45PPDS 333.03.3345PPDS 252.252.52.75DISPLAY PORT2.32.52.7DIFF MOBILE DDR1.719DIFF HSTL I1.41.51.6DIFF HSTL‖1.6DIFF HSTLⅢ1.41.5DIFF HSTL 181.71.819DIFF HSTL‖181.71.81.9D| FF HSTL‖181.71.8DIFF SSTL3 I3.03.3345DIFF SSTL3‖3.03.33.45DIFF SSTL22.32.52.7DIFF SSTL2‖2.32.52.7DIFF SSTL181.7181.9DIFF SSTL18Ⅲ1.7181.9DIFF SSTL15Ⅲ1.4251.51.575Notes:1. LVPECL_33 and TMDS_33 inputs require VCcAUx =3. 3V nominalDS162(1.9) August23,2010www.xilinx.comAdvance Product Specification&A XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsIn Table 9 and Table 10, values for VIL and Vih are recommended input voltages. Values for lot and loh are guaranteed overthe recommended operating conditions at the Vol and Voh test points. Only selected standards are tested. These arechosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum Vcco with therespective Vol and Voh voltage levels shown. Other standards are sample testedTable 9: Single-Ended t/o Standard Dc Input and output LevelsVILHOHOLOHyo StandardV MinV MaxV MinV, MaxV, MaxV MinmAMALVTTL-0.50.82.04.10.42.4Note (2) Note(2)LVCMOS330.82.04.10.4cco-0.4 Note(2) Note(2)LVCMOS250.50.71.74.104Vcco-0.4 Note(2) Note(2)LVCMOS180.50.38084.10.45VcCo-045 Note(2) Note(2)LVCMOS18(-1L0.50.330.714.10.45Vcco-045 Note(2)Note(2)LVCMOS18 JEDEC0.535%Vcco65%Vcco4.10.45CCO0.45 Note(2) Note(2)LVCMOS150.50.38084.125%Vcco75%Vcco Note(3) Note(3)LVCMOS15(-1L0.50.330.714.125%Vcco 75%Vcco Note(3) Note(3)LVCMOS15 JEDEC0.535%Vcco65%VCcO4.125% Vcco 75%Vcco Note(3) Note(3LVCMOS12-0.50.38084.10.4Vcco-0.4 Note(4) Note(4)LVCMOS12(-1L050.330.714.104Vcco-0.4 Note (4) Note(4LVCMOS12 JEDEC-0535% Vcco65%VCCO4.10.4Vcco-0.4 Note(4) Note(4)Pc333-0.530%Vcco50%Vcco Vcco +0.5 10%Vcco 90%Vcco150.5PC|663-0.530%VCCO50%Vcco Vcco+0.5 10%Vcco 90%Vco1.5120-0.525%VCCO70%Vcco4.120%Vcco3SMBUS-0.50.82.14.10.4SDIO0.5125%VCCO75%Vcco4.1125%VCCO75%VCCO0.1MOBILE DDR0.520%VCCO80%VCCO4.110%Vcco 90% vcco0.10.1HSTL I0.5VREF-0.1REF+0.14.10.4CCo-0.48HSTL‖l0.5VREF-0.REF +0.1VF4.10.4Vcco-0.41616HsTLⅢ0.5VREF-0.VREF +0.14.10.4VcCo-0.424HSTL 18-0.5REF-0.1VpVREF +0.14.10.4CCo-0.41HsTL‖180.5VREF-0.VREF +0.14.10.4CCo-0. 42222HsTL川180.5REF0.1VREF +0.14.10.4cco-0. 430-11SSTLEF-02REF+0.2T-0.6TT+0.6sSTL3‖-0.5REF-0.2REF +0.24.1VT-0.8Vm+0.816SsTL-0.5VREF -0.15 VEREF+0.154.1vT-061V+0.618.18.1SsTL2‖-0.5VREF -0.15 VREF+0.154.1TT-0.81Vrr+0.8116.216.2SSTL18-0.5REF-0.125VREF+0.1254.1VT-047Vπ+0476.76.7ssT18‖0.5HEF-0.125VEF+0.1254.1vr-060Vm+06013.4134ssT15‖l0.5REF-0.REF+04.1VIT -O4TT+0.413.4134Notes1. Tested according to relevant specifications2. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA3. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA4. Using drive strengths of 2, 4, 6, 8, or 12 A5. For more information, refer to the Spartan-6 FPGA Selectlo Resources User GuideDS162(1.9) August23,2010www.xilinx.comAdvance Product SpecificationR XILINXSpartan-6 FPGA Data Sheet: DC and Switching CharacteristicsTable 10: Differential /0 Standard Dc Input and Output Levels心以心DICMODOCMNoHOLVV, Min V, Max mV, MinlV10 StandardMaxMaV MinVV, Min V, MaxInaxLVDS 331006000.32.352474541.1251.375LVDS 251006000.32.352474541.1251.375BLVDS 250.32.35240460Typical 50%VccoMINI LVDS 332006000.31.953006001.0MINI LVDS 252006000.31.953006001.01.4LVPECL 3310010000.3281)Inputs onlyLVPECL 2510010000.31.95Inputs onlyRSDS 331000.31.51004001.4RSDS 251000.31.51004001.01.4TMDS 3315012002.73231)400800Vco-0.405Vcc-0.190PPDS 331004000.22.31004000.51.4PPDS 251004000.22.31004000.51.4DISPLAY PORT19012600.32.35Typical 50%VccoDIFF_MOBILE_DDR1000.781.0290%Vcco 10% VccoDIFF HSTL I1000.680.9Vco04|04D| FF HSTL‖1000.0.9Vco-0404DIFF HSTLⅢ1000.680.9Vcc-0.404DIFF_HSTL__18 1000.81.1CCO0.4D| FF HSTL‖181000.8CCo-0.40.4D| FF HSTLⅢ181000.8CCo-0.40.4DIFF SSTL3 I1001.01.9Vm+06V-06D| FF SSTL3‖1001.01.9VT+08V-0.8DIFF SSTL21001.01.5TT+0.61vT-0.61DIFF SSTL2‖1001.01.5V+0.81V-081DIFF SSTL181000.71.1VT+0.47Vm-0.47DIFF SSTL18‖1000.71.1Vm+06Vm-06D| FE SSTL15‖1000.550.95VTT +0.4 VTT-0.4Notes1. LVPECL_33 and TMDS_33 maximum VICM is the lower of V(maximum)or VCCAUx (ViD/2)eFUSE Read enduranceTable 11 lists the minimum guaranteed number of read cycle operations for device dNa and for the aes eFUSe key. Formore information see the spartan-6 FPGA Configuration User guideTable 11: eFUSE Read EnduranceSpeed GradeSymbolDescriptionUnits432L(Min)DNA_CYCLES Number of DNA_PORT READ operations or JTAG ISC_DNA readReadcommand operations. Unaffected by SHIF T operations30,000,000CyclesAES CYCLESNumber of jtag fuse key or fuse cntl read command30,000,000Readoperations. Unaffected by SHIFT operationsCyclesDS162(1.9) August23,2010www.xilinx.comAdvance Product Specification10