MT7620编程手册（完整版）

MT7620 Programming Guide 规格书编程手册开发指导，521页完整版,芯片寄存器功能描述详细说明。适合Linux openwrt 路由器开发参考。RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANYTable of contents1. MIPS 24K PROCESSOR111.1 FEATURES111.2 BLOCK DIAGRAM121.3 MEMORY MAP SUMMARY131.4 CLOCK PLAN141.5 CPU CLOCK MUX152. REGISTERS2.1 NOMENCLATURE162.2 SYSTEM CONTROL2.2.1 FEATURES2.2.2 BLOCK DIAGRAM2.2 3 LIST OF REGISTERS182.2.4 REGISTER DESCRIPTIONS(BASE: 0X1000 0000)192, 3 TIMER4623. 1 FEATuRES462.3.2 BLOCK DIAGRAM4723. 3 LIST OF REGISTERS482.3.4 REGISTER DESCRIPTIONS(BASE: 0X1000 0100)492. 4 INTERRUPT CONTROLLER522. 4. 1 FEATURES522.4.2 BLOCK DIAGRAM532. 4. 3 LIST OF REGISTERS532.4.4 REGISTER DESCRIPTIONS(BASE: 0X 1000 0200)542.5 SYSTEM TICK COUNTER592.5.1 LIST OF REGISTERS592.5.2 REGISTER DESCRIPTIONS(BASE: 0X1000 OD00)602.6 UART612. 6. 1 FEATURES612.6.2 BLOCK DIAGRAM612.6.3凵| ST OF REGISTERS622.6.4 REGISTER DESCRIPTIONS(BASE: 0X1000 05002.7 UART LITE712.7.1 FEATURES712.7.2 BLOCK DIAGRAM2.7. 3 LIST OF REGISTERS2.7.4 REGISTER DESCRIPTIONS(BASE: 0X1000 OCO02. 8 PROGRAMMABLE I/O802.8 1 FEATURES2.8.2 BLOCK DIAGRAM802.8.3 LIST OF REGISTERS812.8.4 REGISTER DESCRIPTIONS (BASE: 0X1000_ 0600)832. 9 C CONTROLLER962.9.1 FEATURES962.9.2 BLOCK DIAGRAN629. 3 LIST OF REGISTERS97PGMT7620V.1.3091112Page 3 of 521RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANY2.9.4 REGISTER DESCRIPTIONS(BASE: 0X1000 09002.10 NAND FLASH CONTROLLER2.10.1 FEATURES1042.10.2 NORMAL MODE FLOW1042.10.3ECC1042.10. 4 LIST OF REGISTERS1072.10.5 REGISTER DESCRIPTIONS (BASE: 0X1000 08001082.11 PCM CONTROLLER1152.11.1 FEATURES1152.11.2 BLOCK DIAGRAM1152.11 3 LIST OF REGISTERS1172.11.4 REGISTER DESCRIPTIONS(BASE: 0X1000_ 2000)1182.115 PCM CONFIGURATION1292.12 GENERIC DMA CONTROLLER1312.12.1 FEATURES1312.12.2 BLOCK DIAGRAM1312.12, 3 PERIPHERAL CHANNEL CONNECTION1322.12, 4 LIST OF REGISTERS1332. 12.5 REGISTER DESCRIPTIONS(BASE: 0X1000 28(1342.13 SPI CONTROLLER2.13.1 FEATURES132.13.2 BLOCK DIAGRAM138213 3 LIST OF REGISTERS1392. 13. 4 REGISTER DESCRIPTIONS(BASE: 0X1000 OB0O1402. 14 12S CONTROLLER1512.14.1 FEATURES1512.14.2 BLOCK DIAGRAM1512.14,312S SIGNAL TIMING FOR I2S DATA FORMAT1522.14, 4 LIST OF REGISTERS1532. 14.5 REGISTER DESCRIPTIONS(BASE: 0X1000 0A0O)1542.15 MEMORY CONTROLLER1582.15.1 FEATURES1582.15.2 BLOCK DIAGRAM1582.15.3 SDRAM INITIALIZATION SEQUENCE1582.15, 4 SDRAM POWER SAVING CONFIGURATION1592.15.5 DDR INITIALIZATION SEQUENCE1602.15. 6 LIST OF REGISTERS1612. 15. 7 REGISTER DESCRIPTIONS(BASE: 0X1000 0300)1622.16 RBUS MATRIX AND QOS ARBITER1762.16.1 FEATURES1762,16.2 BLOCK DIAGRAM1762.16.3 LIST OF REGISTERS1772.16.4 REGISTER DESCRIPTIONS(BASE: 0X1000 04001782. 17 USB HOST conTRoLLER phy1812.17.1 FEATURES1812.17.2 BLOCK DIAGRAM1812.17. 3 REGISTER DESCRIPTION(BASE: 0X101C00001812. 17.4 EHCI OPERATION REGISTERS(BASE: 0X101C 0000182PGMT7620V.1.3091112Page 4 of 521RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANY2. 17.5 OHCI OPERATION REGISTERS (BASE: 0X101C 10001832.1 8 USB DEVICE CONTROLLER1842.18.1 FEATURES1842.18.2 BLOCK DIAGRAM1842.18.3 BULK OUT1842.18.4 LEGACY MODE1852.18.5 AGGREGATION MODE185218.6 DE-AGGREGATION MODE1862.18.7 BULK-OUT AGGREGATION FORMAT1872.18. 8 BULK IN1872.18.9 PDMA DESCRIPTOR FORMAT1882. 18.10 REGISTER DESCRIPTIONS (BASE: 0X1012 00001902.18. 11 USB DEVICE CONTROLLER REGISTERS1902.18.12 UDMA REGISTERS1912.18.1 3 PDMA REGISTERS1922.19 FRAME ENGINE2002.19,1 PSE FEATURES2002.19.2 PPE FEATURES2002.19.3 PACKET DMA(PDMA)FEATURES2002.19, 4 BLOCK DIAGRAM2012,19.5 PDMA FIFO-LIKE RING CONCEPT2022.19.6 PDMA TX DESCRIPTOR FORMAT2032.19.7 PD MA RX DESCRIPTOR FORMAT2052. 19. 8 GLOBAL REGISTERS (BASE: 0X1010 0000)2072.19.9 CPU PORT REGISTERS (BASE: 0X1010 04002142. 19.10 PDMA REGISTERS(BASE: 0X1010 08002212. 19.11 MIB COUNTER DESCRIPTION(BASE: OX1010_ 1000)2332.20 ETHERNET SWITCH2352.20.1 FEATURES2352.20.2 BLOCK DIAGRAM2362.20.3 FRAME CLASSFICATION2362.20.4 SWITCH L2 /L3 ADDRESS TABLE2382.20.5 VIRTUAL LAN242220.6 ACCESS CONTROL LOGIC2452.20.7 ARL REGISTERS (BASE: 0X1011_0000502.20. 8 BMU REGISTERS2892.20.9 PORT REGISTERS2.20.10 MAC REGISTERS3182.20.11 MIB REGISTERS3272.20.12 GSW CONFIGURATION REGISTERS3362.20.13 MDIO CONTROL3452.21 PCI/PCIE CONTROLLER3522.211 BLOCK DIAGRAM3532.21.2 PCIE CONTROLLER ACTING AS A PCIE DEVICE3542.21.3 BLOCK DIAGRAM3552.21.4 PCI/PCIE MASTER ACCESS IN HOST MODE3562.21.5 PCIE CONTROLLER HOST MODE INITIALIZATON EXAMPLE3572.21.6 HOST-PCI BRIDGE REGISTERS (BASE: 0X101400003572.21.7 PCIEO RC CONTROL REGISTERS (BASE: 0X1014_2000)361PGMT7620V.1.3091112Page 5 of 521RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANY2.21.8 MEMORY WINDOWS REGISTERS(BASE: 0X1015_0000)3652.21.9|0W|NDoS(BASE:0×1016_0000)3652.2280211N 2T2R MAC/BBP3662.22. 1 FEATURES3662.22.2 BLOCK DIAGRAM3662.22.3 802 11N 2T2R MAC/BBP REGISTER MAP3672.22. 4 SCH/WPDMA REGISTERS(BASE: 0X1018 0000)3682.22.5 PBF REGISTERS (BASE: 0X1018_0000)3802.22.6 RF TEST REGISTERS(BASE: 0X1018 00003902.22. 7 MAC REGISTERS (BASE: 0X1018 0000)3912.22. 8 MAC TIMING CONTROL REGISTERS(BASE: 0X101800004072.22.9 MAC POWER SAVE CONFIGURATION REGISTERS (BASE: 0X1018 0000)4142.22.10 MAC TX CONFIGURATION REGISTERS(BASE: 0X1018 00004192.22. 11 MAC RX CONFIGURATION REGISTERS (BASE: 0X1018_0000)4472.22.12 MAC SECURITY CONFIGURATION REGISTERS (BASE: 0X1018 0000)4552.22. 13 MAC HCCA/PSMP CONTROL STATUS REGISTERS (BASE: 0X1018 00004562. 22 14 MAC STATISTIC COUNTERS (BASE: 0X1018 00004602.22. 15 MAC SEARCH TABLE (BASE: 0X1018 18004693. SECURITY ENTRY FORMATS AND KEY TABLES4713.1 SECURITY ENTRY FORMAT TABLES (BASE: 1018.0000, OFFSET: 0X40004713.1.1 SECURITY KEY FORMAT (8DW4713.1.2 IV/EIV/WAPI PN FORMAT (4DW4713.1.3 WCID ATTRIBUTE ENTRY FORMAT(1DW)4723.1.4 SHARED KEY MODE ENTRY FORMAT(IDW)4733.2 SECURITY TABLES OFFSET: OX4000)4743. 3 SECURITY TABLE MAP4743.3. 1 PAIRWISE KEY TABLE(OFFSET: 0X4004753.3.2 IV/EIV TABLE(OFFSET: 0X60004753.3.3 WCID ATTRIBUTE TABLE OFFSET: 0X68004753.3.4 SHARED KEY TABLE(OFFSET: 0X6C00)4753.3.5 SHARED KEY MODE ( OFFSET: 0X7000)4763.3.6 SPARE MEMORY SPACE MODE OFFSET: OX7010 TO OX73EC4763.3.7 SHARED KEY MODE EXTENSION(FOR BSS_IDX=& TO 15)(OFFSET: OX73FO)4773.3. 8 SHARED KEY TABLE EXTENSION (FOR BSS IDX=8 TO 15)(OFFSET: 0X74004773.3.9 WAPI PN TABLE(EXTENSION OF IV/EIV TABLE)(OFFSET: 0X78004784. TX/RX DESCRIPTORS AND WIRELESS INFORMATION4794.1 TX DESCRIPTORS AND FRAME INFORMATION4794.1.1 TXD FORMAT4804.1.2 TX WIRELESS INFORMATION4824.2 RX DESCRIPTORS AND WIRELESS INFORMATION4864.2. RXD FORMAT4874.22 RXINFO FORMAT48842, 3 RXWI FORMAT4904 3 BRIEF PHY RATE FORMAT AND DEFINITION49243.1 MODULATION AND CODING SCHEME4935. SD HOST CONTROLLER4955.1 FEATURES495PGMT7620V.1.3091112Page 6 of 521RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANY5.2 SD HOST BLOCK DIAGRAM4955.2.1 BASIC DMA MODE4965.2.2 LINKED-LIST BASED DMA MODE4965.2.3 DMA GENERIC PACKET DESCRIPTOR(GPD)FORMAT4985.2. 4 DMA BUFFER DESCRIPTOR(BD)FORMAT5005.2.5 REGISTER DESCRIPTION(BASE: 0X1013 00005016. LIST OF REGISTERS5027. ABBREVIATIONS5188. REVISION HISTORY521PGMT7620V.1.3091112Page 7 of 521RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANYTable of FiquresFIGURE 1-1 MT7620 BLOCK DIAGRAMFIGURE 1-1 MIPS 24KEC PROCESSOR12FIGURE 1-2MT7620 CLOCK DIAGRAM14FIGURE 1-3 CPU CLOCK MUX15FIGURE 2-1 SYSTEM CONTROL BLOCK DIAGRAM17FIGURE 2-2 TIMER BLOCK DIAGRAMFIGURE 2-3 INTERRUPT CONTROLLER BLOCK DIAGRAM53FIGURE 2-4 UART BLOCK DIAGRAMFIGURE 2-5 UART LITE BLOCK DIAGRAMFIGURE 2-6 PROGRAMMABLE I/O BLOCK DIAGRAMFIGURE 2-7 12C CONTROLLER BLOCK DIAGRAM96CIGURE 2-8 NORMAL MODE FLOW104FIGURE 2-9 24-BIT ECC GENERATED FROM 512-BYTE DATA .........105FIGURE 2-10 HARDWARE ECC DETECTION FLOWCHART106FIGURE 2-11 PCM CONTROLLER BLOCK DIAGRAM115FIGURE 2-12 GENERIC DMA CONTROLLER BLOCK DIAGRAM.131FIGURE 2-13 SPI CONTROLLER BLOCK DIAGRAM138FIGURE 2-14 S TRANSMITTER BLOCK DIAGRAM151FIGURE 2-15 12S TRANSMIT/RECEIVE152FIGURE 2-16 SRAM/SDRAM CONTROLLER BLOCK DIAGRAM158FIGURE 2-17 QOS ARBITRATION BLOCK DIAGRAM176figure 2-18 USB HosT contROLLER phy block diagram181FIGURE 2-19 USB DEVICE CONTROLLER BLOCK DIAGRAM184FIGURE 2-20 DE-AGGREGATION FLOW186FIGURE 2-21 BULK-OUT AGGREGATION FORMAT187FIGURE 2-22 PD MA TX DESCRIPTOR FORMAT188FIGURE 2-23 PD MA RX DESCRIPTOR FORMAT189FIGURE 2-24 USB DEVICE REGISTER MAPPING190FIGURE 2-25 FRAME ENGINE BLOCK DIAGRAM201FIGURE226 PDMA FIFO-LIKE RING CONCEPT,……202FIGURE 2-27 PDMA TX DESCRIPTOR FORMAT垂垂垂203FiGURE 2-28 PDMA RX DESCRIPTOR FORMATFIGURE 2-29 ETHERNET SWITCH BLOCK DIAGRAM236FIGURE 2-30 PHY ADDRESS DECODING(O)345FIGURE 2-31 PHY ADDRESS DECODING()FIGURE 2-32 PCIE HOST TOPOLOGY352FIGURE 2-33 PClE AP MODE353FIGURE 2-34 PCIE CONTROLLER BEHAVING AS A PCIE ENDPOINT354FIGURE 2-35 PCIE RC/EP BLOCK DIAGRAM灬355IGURE 2-36 PClE MEMORY SPACE PROGRAMMABLE MAPPING356FIGURE 2-37 PCI MEMORY SPACE FIXED MAPPING356FIGURE 2-38 I/O SPACE PROGRAMMABLE MAPPING356FIGURE 2-39 802. 11N 2T2R MAC/BBP BLOCK DIAGRAM366FIGURE 2-40 802. 11N 2T2R MAC/BBP REGISTER MAP....∴367FIGURE 3-1 SECURITY KEY MEMORY LOCATIONS474FIGURE 4-1 TXD AND TX FRAME INFORMATION479FIGURE4-2 TXD FORMAT∴…480FIGURE 4-3 RX DESCRIPTOR RING486PGMT7620V.1.3091112Page 8 of 521RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANYIGURE 4-4 RX DESCRIPTOR FORMATFIGURE45 RXINFO FORMAT.……,………488FIGURE 4-6 RXWI FRAME FORMAT垂垂垂490FIGURE 5-1 SD HOST BLOCK DIAGRAM495FIGURE 5-2 BASIC DMA496FIGURE 5-3 DESCRIPTOR DMA497FIGURE5-4 GPD FORMAT∴498FIGURE 5-5 BD FORMAT500PGMT7620V.1.3091112Page 9 of 521RalinkMT7620 PROGRAMMING GUIDEA MEDIATEIntegrated 802.11n MAC/BBP and 2. 4 GHz RF/FEM Router-on-a-ChipCOMPANYList of tablesTABLE 2-1 UART LITE INTERRUPT PRIORITIES74TABLE 2-2 PD MA RX FIELD DESCRIPTIONSTABLE 2-3 RULE MASK247TABLE 2-4 RATE CONTROL247TABLE25 RULE CONTROL∴247TABLE 2-6 TRTCM METER TABLE249TABLE 2-7 ADDRESS TABLE WRITE DATA REGISTER: MAC ADDRESSTablE 2-8 ADDRESS TABLE WRITE DATA REGISTER: DIP ENTRY.275TABLE 2-9 ADDRESS TABLE WRITE DATA REGISTER: SIP ENTRY275TABLE 2-10 ADDRESS TABLE READ DATA REGISTER: MAC ENTRY277TABLE 2-11 ADDRESS TABLE READ DATA REGISTER: DIP ENTRY278TABLE 2-12 ADDRESS TABLE READ DATA REGISTER: SIP ENTRY∴278TABLE 2-13 VLAN AND ACL WRITE DATA-I REGISTER VLAN ENTRY279TABLE2-14 VLAN AND ACL WRITE DATA- REGISTER: ACL RULE TABLE,……………280TABLE 2-15 VLAN AND ACL WRITE DATA-I REGISTER ACL RULE MASK.......w.4280TABLE 2-16 VLAN AND ACL WRITE DATA-I REGISTER: ACL RATE CONTROL280TABLE 2-17 VLAN AND ACL WRITE DATA-I REGISTER ACL RULE CONTROL280TABLE 2-18 VLAN AND ACL WRITE DATA-I REGISTER: TRTCM METER TABLE281TABLE 2-19 VLAN AND ACL WRITE DATA-II REGISTER: VLAN ENTRYTABLE 2-20 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE TABLE281TABLE 2-21 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE MASK281TABLE 2-22 VLAN AND ACL WRITE DATA-II REGISTER: ACL RATE CONTROL281TABLE 2-23 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE CONTROL281TABLE 2-24 VLAN AND ACL WRITE DATA-II REGISTER: TRTCM METER TABLE282TABLE 2-25 DEBUG CONTROL REGISTER: DEBUG ID AND CONTROL287TABLE 2-26 PCI/ PCIE SCENERIO AND RELATIVE CONTROL REGISTER SETTINGS354TABLE 2-27: 0X1398 TX RATE LUT EN=OAND MULTI MAC ADDRESS =0469TABLE 2-28: 0X1398 TX RATE LUT EN=1 AND MULTI MAC ADDRESS =0TABLE 2-29: 0X1398 TX RATE LUT EN= 1 AND MULTI MAC ADDRESS=1470TABLE 3-1 IV/EIV FORMATTABLE 3-2 WAPI PN FORMAT…472TABLE 3-3 WCID ATTRIBUTE ENTRY FORMAT垂垂垂473TABLE 3-4 SHARED KEY MODE ENTRY FORMAT(lDW)473TABLE 3-5 PAIRWISE KEY TABLE ( OFFSET: 0X4000475TABLE 3-6 IV/EIV TABLE(OFFSET: 0X6000)475TABLE 3-7 WCID ATTRIBUTE TABLE(OFFSET: 0X6800)TABLE 3-8 SHARED KEY TABLE (OFFSET: 0X6COO476TABLE 3-9 SHARED KEY MODE(OFFSET: 0X7000)476TABLE 3-10 SHARED KEY MODE EXTENSION(FOR BSS IDX=8 TO15)(OFFSET: OX73FO)477TABLE 3-11 SHARED KEY TABLE EXTENSION(FOR BSS IDX=8 TO15)OFFSET: 0X7400478TABLE 3-12 WAPI PN TABLE(EXTENSION OF IV/EIV TABLE)(OFFSET: 0X73FO)478TABLE 4-1 TX DESCRIPTOR FORMAT FIELD DESCRIPTIONS481TABLE 4-2 TXWI FRAME FORMAT482TABLE 4-3 TXWI FIELD DESCRIPTIONS485TABLE 4-4 RXWI FIELD DESCRIPTIONS∴491TABLE 4-5 BRIEF PHY RATE FORMAT AND DEFINITION492TABLE 4-6 MODULATION AND CODING SCHEME494PGMT7620V.1.3091112Page 10 of 521