at91sam9260 nandflash说明文档

at91sam9260 关于nand外设的说明文档，9260的data sheet关于nand介绍太少了，这片文章是atmel公司专门为支持nandflash出的说明文档。Application NoteNAND Flash typically contains blocks that contain errors and cannot be used. A check must bedone by software to list and maintain a table of bad blocks. Data integrity is achieved by usinghardware or software techniques, such as ECC, that check and correct bad data2.2.3PerformancesFurther differences between NOR and NANd Flash can be found in read /write performancesTable 2-1 shows random access time for NOR Flash specified at 0.09 uS, whereas NAnd ran-dom access is significantly slower--25 us- for the first byte. Once the initial access has beenmade, however, the remaining 2, 1 11 bytes are shifted out of NAND at only 30 ns per byte. Thisresults in a bandwidth of more than 23 mb/s for 8-bit y/os or 37 Mb/s for 16-bit l/osThe real benefits for NAND Flash can be found in the faster program and erase times, sinceNAND provides over five megabytes per second of sustained write performance. The blockerase times are an impressive 2 ms for NAND versus 200 ms for NORTable 2-1. differences in performanceNAND FlashNOR FlashCharacteristicsK9F2G08UOMAT49Bv16X4-9025μs( first byte)Random access read30 ns each for remaining 2111 0.09 usbytesSustained read speed(sector basis)37 Mbytes/s11 Mbytes/sRandom write speed300 us/2, 112 bytes20 us/bytesSustained write speed(sectorbasis5 Mbytes/s0.05 Mbytes/sErase block size128 Kbytes64 KbytesErase cycles100,000to1,000,00010.000to100000Erase time per block2 ms200ms2.2.4ConclusionTable 2-2 summarizes nand/nor advantages and disadvantagesTable 2-2. NAND/NOR ComparisonNANDNORFast writesFast erasesRandom accessAdvantagesLower bit costByte writes possibleHigher densitySlow random accessSlow writesDisadvantagesByte writes difficultBad blocks management and ECCSlow eraserequiredFile(disk) applicationsApplicationsVoice data video recorderExecute directly from non volatilememoryAny large sequential dataClearly, NAND Flash has several significant positive attributes. The one negative attribute is thatit is not well-suited for direct random accessAmEL6255B-ATARM-26-Jun-0gAm耳NAND is available in large capacities and is the lowest cost Flash memory available todayNAND is used in virtually all removable cards for cost/density reasons: USB Cards, MemoryStick, MMC Multimedia Card, SD Secure Digital, CF Compact Flash3. Bad Block Management and Error Corrected Code(Ecc)3.1 Definition of“BadB|ock”By default, nand devices contain invalid blocks which have one or more invalid bitsFurthermore, since the first memory block(physical block address ooh)in nand devices isguaranteed to be free of defects (up to 1,000 PROGRAM/ERASE cycles), the first 8 Kb of Flashmemory can safely be used for system bootstrapping functions3.2 Software ConsiderationsTo avoid writing to and reading from bad memory blocks, system software must create a map ofnvalid memory blocks. If the application code executes from RAM rather than Flash memorysystem software bad-block mapping is only necessary at boot time and during Flash storageupdatesAll device locations are erased(FFh for X8, FFFFh for X16) except locations where the invalidblock information is written prior to shipping. The invalid block status is defined by the 1st byt(X8 device)or 1st word (X16 device )in the spare areaThe 1st or 2nd page of every invalid block has non-FFh(X8)or non-FFFFh(X16) data at the col-umn address of 2048(X8 device)or 1024(X16 device). Since the invalid block information isalso erasable in most cases, it is impossible to recover the information once it has been erasedTherefore, the system must be able to recognize the invalid block(s)based on the original invalidblock information and create the invalid block table via the flow chart in Figure 3-1Figure 3-1. Bad Block Recognition Flow ChartStartSet block address= 0Increment block addressCheck"FFh or FFFFh)"at the column addressCreate(or updateNo:048(X8 device)or 1024(X16 device)Check"FFh of the 1st and 2nd page in the blockInvalid Block(s) Tableor fffFh?NoLast blockesEndApplication Note6255B-ATARM-26-Jun-09Application NoteImportant Note: Any intentional erasure of the original invalid block information is prohibited3.3 ECCNAND devices are subject to data failures that occur during device operation. To ensure dataread/write integrity, system error-checking and correction(ECC) algorithms must be implemented. Depending on the at91 product, the eCc algorithm must be calculated by software orcan be generated by the embedded hardware ECC controller. The ECc controller is capable ofsingle bit error correction and 2-bit random detection. When nand has more than 2 bits oerrors, the data cannot be corrected. This controller allows ECC management without CPU inter-vention and thus improves the total bandwidth of the system4. NAND Flash Signals4.1 Bus OperationThe bus on NAND Flash devices is internally multiplexed Data I/O, addresses, and commandsall share the same pins. I/0 pins. I/O[15: 8] are used only for data in the x16 configurationAddresses and commands are always supplied on I/O[7: 0The command sequence normally consists of a command latch cycle, an ADDRESS LATCHcycle, and a data cycle either read or Write4.2 Control signalsThe signals CE#, WEt, RE#, CLE and ALE control Flash device READ and WRITE operationsCE# is used to enable the device. When Ce# is low and the device is not in the busy state theFlash memory accepts command, data, and address informationWhen the device is not performing an operation, the CE# pin is typically driven HIGH and thedevice enters standby mode. The memory enters standby if ce goes HIGH while data is beingtransferred and the device is not busyA subset of NANd Flash supports the CE# "Don't Care"operation allowing the NANd Flash toreside on the same asynchronous memory bus as other Flash or SRAM devices. Other deviceson the memory bus can then be accessed while the nand Flash is busy with internal operations. This capability is important for designs that require multiple memory devices on the samebus4.3 Commands(ALE=0, CLE =1)All the NAND operations(except READ STATUS and RESET commands)consist of a com-mand write cycle followed by address write cycle the rEad status command does not havean address write cycle. The command is transferred into the NAnd command register followedby the start address, for the read or program operation, latched into the address registerCommands are written to the command register on the rising edge of WE# when·CE# and ale are lowCLE is highCommands are input on l/o[7: 0]only. For devices with a X16 interface, I/O[15: 8]must be writtenith zeros when issuing a command56255B-ATARM-26-Jun-0gAm耳4. 4 Address(ALE =1, CLE=0)Addresses are written to the address register on the rising edge of WE# when·CE# and cle are|oW° ALE is highAddresses are input on I/o[7: 0]only. For devices with a x16 interface, 170[15: 8] must be writtenwith zeros when issuing an address. Generally all five ADDRESS cycles are written to thedevice4.5 Data(ALE =0, CLE=0Data is written to the data register on the rising edge of WE# when CE#, CLE, and ALE are lowData is input on l/o[7: 0] for x8 devices, and 1/0[15: 0] on x16 devices4.6 Ready /BusyThe R/B# output provides a hardware method of indicating the completion of a pro-GRAM/ERASE/READ operation. The signal is typically high, and transitions to low after theappropriate command is written to the device. a dedicated Plo should be assigned to this signalwith a pull-up resistor for proper operation. Alternatively, the READ StaTUs command can beused by the software4.7 ExampleThe following waveforms shows the successive accesses: COMMAND Latch, ADDRESS Latchand datA Output with a"ce dont Care" NAND. notice that no command can be sent to theNAND Flash during tR, because it is busyFigure 4-1. Page READ OperationCLEtcHA△A△A△ aAAAaaREtALE/VIVIVIVIIWE却rAddress (5 Cycle30hData outoutDon t Care6 Application Note6255B-ATARM-26-Jun-09Application Note5. AT91 EBI NandFlash LogicThe nand Flash logic is driven by the Static Memory Controller (SMC)on the NcS3 addressspace Programming the CS3a field in the EBl CSA Register in the Bus Matrix User Interface tothe appropriate value enables the nand Flash logic. For details on this register, refer to the busMatrix User Interface section in the product datasheet. Access to an external NANd Flashdevice is then made by accessing the address space reserved to ncs3(i.e, between0X40000000 and 0X4 FFF FFFF)The nand Flash Logic drives the read and write command signals of the Smc on the nandoeand NANDWE signals when the NCs3 signal is active. (refer to the Static Memory Controllersection in the product datasheet)The address latch enable and command latch enable signals on the NAND Flash device aredriven by address bits A22 and A21 of the EBl address bus. The command, address or datawords on the data bus of the NAnd Flash device are distinguished by using their address withinthe NCS3 address space. The chip enable(CE) signal of the device and the ready/busy(R/B)signals are connected to PlO linesTwo NAND Flash types exists, those who are "ce don 't care"and those who are notFor "Ce don' t care"NAND, the chip enable state is dont care during the busy period precedingthe data read cycle. Thus allowing this flash to be connected to active memory buses such asthe at91 memory busFor standard NAND, the CE signal remains asserted even when NCS3 is not selected, preventng the device from returning to standby mode. In this case, a Plo line should be dedicated todrive the Chip enable signalUnlike the at91SAM9261, where A21 and A22 are not specifically dedicated to NANd flashALE and CLE signals, on the AT91 SAM9260 A21/ALE and A22/CLE are the signals mandatoryto drive the nand flash and Ecc controller. Another combination of addresses prevent usingthe ecc controller with the nand flashTable 5-1. EBl Signals Example for AT91SAM9261NameFunctionTypeActive levelNANDCSNAND Flash Chip select LineOutputLOWNANDOENANd Flash Output enableOutputLOWNANDWENAND Flash write enableOutputLoWCLE(A21)(3)Command latch enableOutputHighALE(A22)(4)Address Latch enableOutputHighPIOX/CEChip Enable(1)(2)OutputLOWPlOy/RDY/BSYReady/Busy(1)InputLOWNotes: 1. Any free Plo can be used for this purpose2. For standard nand3. For aT91SAM9261 the address bit A21 is arbitrarily dedicated to CLE4. For at9 1 1 the address bit a22 is arbitrarily dedicated to ALe6255B-ATARM-26-Jun-0gAm耳Table 5-2. EBl Signals Example for AT91SAM9260NameFunctionTypeActive LevelNANDCSNAND Flash Chip Select LineOutputLOWNANDOENAND Flash Output EnableOutputNANDWENAND Flash Write EnableOutputA22/CLECommand latch EnableOutputHighA21/ALEAddress Latch EnableOutputignPIOX/CEChip Enable(1)(2OutputPlOY/RDY/BSYReady/Busy(1)nputNotes: 1. Any free Plo can be used for this purpose2. For standard nandTable 5-3ALE/CLE ManagementAT91SAM9261 MemoryAT91SAM9260 MemoryALE CLEAddress offsetAddress offsetNAND Register Selected00x0000000x000000DATA register00110x2000000x400000COMMAND register00×4000000×200000ADDRESS register0x6000000×600000Undefined(Dont use)Figure 5-1.CE dont care"and standard NANd Flash Application EXample8 Application Note6255B-ATARM-26-Jun-09■ Application Note6. AT91 System Initialization for a K9 F2G08UOM Device6.1 ClocksThe system is running at full speed, this means 198 MHz for the processor and 99 MHz for theBus. The EBl NCS3 is to be assigned for NANd Flash usageTable 6-1. System ConfigurationDescriptionSettingsRegister/fieldValSystemPLL frequency198 MHzPMC PLLAR0x20603F09Processor/bus clock198/99MHzPMC MCKR0x00000102EBl Chip select AssignmentNANDEBI CSAEBI CS3A0x86.2 PIOs6.2.1Standard nandTwo PlO lines are needed for CE and RDY/BSY. NANDOE(PCo)and NANdWE(PC 1)are tobe configured for NAND Flash usageTable 6-2. Peripheral Configuration for Standard NAnd on at91SAM9261DescriptionSettingsAt91 ibV3 FunctionNANDOE and nandwe areAT91F PIO CfgPeriph(AT91C BASE PIOC, (AT91C PCO SMOErespectively PCO and PC1OutputAT91C PCI SMWE),0);PC14 is CE(1)OutputAT91F PIO CEgOutput (AT91C BASE PIOC, AT91C PIO PC14)PC 15 is RDY/BSY(1)InputAT91F PIO CEgInput(AT91C BASE PIOC, AT91C PIO PC15)Enable PlO clock(1)At91F PIOC CfgPMC (Note: 1. Any free plo can be used for this purpose6.2.2ce dont care”NANDOne Plo line only is needed, for RDY/BSY. ncs3 has the NAndcS function. On theAt91SAM9260 the ncs3 is multiplexed with a Plo line allowing standard nand Flash and"CEdon' t care" device support without any hardware modificationTable 6-3. Peripheral Configuration for "ce dont Care"NAND on AT91SAM9260DescriptionSettingsaT91 ibv functionNCS3 is CEAT91F PIO CEgPeriph(AT91C BASE PIOCOutputAT91C PC14 NCS3 NANDCS, 0)PC13 is RDY/BSY(1)InputaT9lF PIO CfgInput(At9lC BASE PIOC, Ar9lC PIO PC13)Enable PlO clock(1)AT91F PIOC CEgPMC (Note: 1. Any free Plo can be used for this purpose6255B-ATARM-26-Jun-0gAm耳6.3 SMC TimingsThe k 9F2G08UOM is a 256 mb device connected with an 8-bit data bus widthAn accurate one-to-one comparison is necessary between NandFlash and smc waveforms fora complete SMC contiguration Figure 6-1 and Figure 6-2 show two cases that highlight all therequired timings.Figure 6-1. COMMAND LATCH and ADDRESS LATCH CycleCLEXWE#tALS'ALHALE ANote: x16: Vo[15: 8] must be set toO.Figure 6-2. SERIAL ACCESS Cycle after READYEADOUTOUTThese timings are summarized in Table 6-410 Application Note6255B-ATARM-26-Jun-09