xilinx选型指南

xilinx选型指南全系列xilinx选型指南全系列Virtex-5 Family FPGAsVIRTEXVirtex-5 LX FPGAsVirtex-5 LXT FPGASOptimized for High-performance LogicOptimized for High-performance logic(1.vowith Low-power Serial Connectivity(1.0 Volt)Part Number XC5VLX30 XC6VLX50 XC5VLX86 XC6VLX110 XC5VLX155 XC6VLX220 XC5VLX330 XC5VLX20T XC6VLXSOTXC6VLX6OTLXB6T XC6VLX110T XC6VLX165T XC5VLX220T XC6VLX830TEasy Pa: h" Cost Reduction Solutions (1XCESVLX85 XCE5VLXI 10 XCE5VLX 155 XCE5VLX220 XCE5VLX330XCEVLXT85T XCE5VLXI ICT XCE5VLX 155T XCE5VLX220T XCE5VLX330TSlices (2,4,8007,2001296034,560518403120480012,96024,32034,5Logic Resourcesngic: Cells(33072046.0808944155648291.18433177630.72c829441556481184331776Flip-Flcps19,200,80518497,28012480o0051,8403B,240m D stributed RAM(Kbits22801,640228Block RAM/FIFO W/ECC(36Kbis each)1922B8148212而dRM_1217684564668126912108661262106868600220216Digital Cock Managers(DCM)42412K ResourcesPhase Locked Loop(PLL): PMCD661266366Maximum Single-Ended Pins800120172363480630I/O Resources , eMaximum Differentia I/O PairsBC60C1802403403404801/QStandardsHT. IVnS, IVDSFXT, RSDS, RIVDS, Ull'MnS, IVPFCI, IVCMOS33 IVCMOS95, IVCMOS1R, IVCMOS15, IVTTL, PCIR3, PCI66,SST 2I SSTI 2 IL SSTI 181 SSTI 1F IlDSPABE Slices4B48412812PowerPC 440 Processor BlocksEmbedded (eFCl Express"Endpoint BlocksHard IP10/100/1000 Ethernet MAC BlocksRocketIO GTP Low-Power Transceivers8Rocketlo"GTX High-Speed TransceiversSpeed GracesCmne1231223,231,231231.212|121231,-2,3-1.-2.3-1.-2.-3-1,-2.-3-1.21,-2austria1.-21.-21.-21.21-21.-21.-21,21.-21.21Configuration Memory(Mbits)12.621.953279.89.44.123.431.243.1552827Package nAreaAvailable User 1/0: SelectIO Interlace Pins(GTP/GTX Serial Transceivers)FFA Packages(FF flip-chip fine-pitch BCA (1.0 mm ball spacing)FF32419 x 19 mm22cFF116336 x 36 mm800F176C42.6x42.6mm8008001200FF32319 x 19 mm172(4)172(4FF665360(8)360(8)35 x 35 mm48012)480(12)40(16)640(16)FF173842.5x425mm680(16)630(16)680(16)960(24)FF115635 x 35 mmF1759425x425mmNotes: 1. Easy Path solutions provide a conversion free and low risk path for volume production2. A single Virtex-5 FPGA comprises two slices, with each containing four 6-input LUTs and four Flip-Flops( twice the number found in a Virtex-4 slice), for a total of eight 6-LUTS and eight Flip-Flops per CLB3. Virtex-5 FPGA logic cell rat ings reflect the increased logic capacity offered by the new 6-input LUT architecture4. Digitally Controlled Impedance(DCl] is avaiable on I/Os of all devices5. /0 standards supported HT, LVDS. LVDSEXT, RSDS BL/DS. ULVDS, LVPECL, L/CMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVTTL PCI33, PC136, PCI-X, GTL. GTL+, HSTL I(1.2v. 1. 5V. 1. 8V). HSTL ll (1.5V, 1.8 HSTL Ill (1.5V. 1.8V). HSTL IV[1.5V.1.8V). SSTL2 l. SSTL2 ll, SST_18 L, SSTL186. One system moni or block included in all devicesImportantVerityalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.com/virtex5≤XL|NXXILINX VIRTEX-5 FAMILY FPGAS -2Q2009≤XLNXXILINX VIRTEX-5 FAMILY FPGAs -2Q20094Virtex-5 Family FPGAsVIRTEXVirtex-5 SXT FPGAsVirtex-5 FXT FPGAsVirtex-5 TXT FPGAsOptimized for DSP with Low-powerOptimized for Embedded Processing withSerial Connectivity (1.0 Volt)High-Speed Serial Connectivity(1.0 Volt)Bandwidth (1.0 Volt)Part Number XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T XC5VFX3DT XC5VFX70T XC5VFX100TXC5VFX130TXC5VFX200T XC5VTX150T XC5VTX240TEasyPath"Cost Reduction Solutions(XCESVSXSOT XCE5VSX95T XCE5VSK24CTXCESVFXT7OTXCE5VEXT100TXCESVFXT130TXCESVFXT200] XCES/TXT1EOT XCESVTXT240TSlices514405,1201,2016,00025,48023,20037440Logic ResourcesLogic Cells (3)3481652224396163276871,6B0102400131,072148,480239,61CLB Flip-Flops21,76032.64C5888C49,76044.8064,00081920122883149,760Maimum Distributed RAM(Kbits)4.2001,5B020150240Memory ResourcesBlock RAM/FIFO w/FCC(36Khits each)5166814824602Total Block RAM(Bite)30241857653288.20872816,41611664Digitel Clock Managers(DCM)121241212Clock ResourcesPhase Locked Loop(PLL)'PMCDaxmum S ngle- Ended Pins1/O ResourcMaximum Differential 1/O Pairs320I/O Standards HT, LVDS, LVCSEXT, RSDS, BLVDS, ULVDS, LVPECL, LVCMOS33, LVCMOS26, LVCMOS13, LVCMCS16, LVTTL, PCl3, PCI66, PCI-X, GTL, GTL+, STL I(1.2V, 1.5V,1.8V)HSTL ll(1. 5V,1.6V), HSTL lll(1.5V, 1.81), HSTL I/(1. 5V,1.8V, SSTL2 1, SSTL2 ll, SSTL 18 SSTL18 llDSP∠8 E Sices64PowerPC 440 Processor Blocks222Embedded ( o?PCI Express" Endpcint Blocksard IlResources10/100/1000 Ethernet MAC BlocksRocketIO GTP Low-Power Transceivers16RocketIO GTX High-Speed TransceiversB16CommercialSpeed Grades1,-2,-31,2,-3-1,-2312912912,21,-2ConfigurationConfiguration Memory(Mbits3420.079?13.e27.139.449.365.8Package (7AreaAvailable User 1/0: SelectIo Interface Pins(GTP/GTX Serial Transceivers)FFA Packages(FF): flip-chip fine pi: ch BGA (1.0 mm ball spacing)FF:15335x 35 mmFF176042.5×425mmFF32319x19FF665360()360(3)FF113636 x 35 mm480(12)640(16)640(16)640(16)FF173842.6x42.6mmc60(24680(16)840(20)060(24)FF35x35 mmFF175942.5x425mn680(48)Easy Fath"solutions provide a conversionrfree and low risk path for volume production2.A sincle Virtex-5 FPGA ccmprises two slices, wih each containing four 6-inpu: LUTs end four Flip-Flops(wise the nunber found in a Virtex-4 slice). for a to al of eight 6-LUTs and eight Flip-Flops per CLB.3. Virtex-5 FPGA logic cell ratings reflect the increased logic capacity offered by the new G-inout LUT architecture4. Digitally Controlled Impedance(dCi) is ava lable on l/Os of all devices5. IO standards suppoted IIT, LVDS, LyD3DXT RGDS, DLVD, ULVDG, LVPCCL LVCMOG33, LVCMOG25, LVCMOS1E, LCMOS15, LVTTL, PCI3G, FCIGG, PClK, GT, GTL+. I IGTL I(1.2V, 1.5V, 1. V), I IGTL I (1.5V 1.0V), I IGTL l (1.5V, 1 0V),HSTL N( bV, 1.8V), SSTL2 1, SSTL2 L, SSTL18, SSTL136.07. All products available Po-tree and RoHS- Compliant.ImportantVerifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.com/virtex5Virtex-4 Family FPGasVIRTEXVirtex-4 LX FPGAsVirtex-4 SX FPGAsVirtex-4 FX FPGAsOptimized for High-performance logic(1.2 Volt)Optimized for dsp(1.2 Volt)Optimized for Embedded Processing Serial Connectivity (1.2 Volt)Part Number XC4VLX15XC4VLX25 XC4VLX40 XC4VLX80 XC4VLX100XC4VLX1 60 XC4VLX200 XC4VSX25XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20XC4VFX40 XC4VFX60XC4VFX 100 XC4VFX140Easypath" Cost Rcduction Solutions (1)XCE4VLX40 XCE4VLX60 XCE4VLXBO XCEAVLX100 XCE4VLX160 XCE4VLX200XCE4VSX3E XCE4VSX66CE4VFX40 XCE4VFX60 XCE4VFX100 XCE4VFX140slices5,1441843226,6243584049,1526758415.36054285441,62423,28042,176Logic Resources72110.59206420044812,31219,22494,39CLB Flip-Flop12,28821504368645324871.68098,304135.16178.176204803072049,15210,9441708850,56084,352Maximum Distributed RAM(Kbi:s)15681.05638413495659987ResourcesBlock RAM/FIFO w/ECC(18 Kbits cach)Tcta Block RAM(Kbi s)8641,2963.60043205,184604834565706481.22425924,1769936ClockDigital Clock Managers ( DCM)8ResourcesPhase-matched Clock Dividers(PMCD)8040日88Maximum Sincle-Ended 1/Os320448640640960320448640320448768896Maximum Differential 1/O Pairs1604801601e038481/0 StancardsLDT-25, LVDS-25, LVDSCXT-25,0LVDS-25, ULVDS-25, LVPCCL-25, LVCMCS25, LVCMO310, LVCNOS15, PCI33, LV/"L, LVCMOS33, PCI-X, FCIGG GTL CTL+, ISTLI (1.5V, 1.0V), I ISTL 15V/, 1.0V). I ISTL ll(1.5V,1.0V), IISTLIV(1.5V.1.0V), SSTL2L, SSTL 21l,SSTL101, SS. llDSP48 Slices512Embedded HardPowerPC Processor BlocksIP Rescurces10/100/1000 Ethernet MAC Blocks4Rocketlo Serial TransceiversCommercial0-11.-12-10.-11-10,-11,-12-10,·11,1210,-11,-12-10,-11,-12-10,11,-12-10,-111101210.0121112-10.12-10-12-10-12-10,121011Speed Grades-10,-1110.-110.-1110,·1110.-1110,-110,-1110.-1110.-1110.-11O,-1110,-1110ContigurationConfiguration Memory(Nbi:s)4.8812.31773074C.351.43.12277214.921.033.C473PackageAvailable User 1/O: SelectIO Interfaces Pins( RocketIo Transceivers)SFA Packages(SF): flip-chip fine- pi ch BGA (0. 8 mm ball spacing)SF36317 x17 nmFFA Packages(FF): flip-chip fine-pitch BGA (1. C mm ball spacing)FF66627 x 27 mm320320F114835 x 35 mm640640F15134040 mm960960FF37227 x 27 mm2(12)3E2{12)F115235x3(12)576(16)576(20)FF151740x40 mm768(20)768(24)Notce: 1. Easy Path" solutions providc a conversion-frcc and low-ris< patn for volumc production2. Each slice comprises two 4-input lagic function genera: ors (LUTs), two storage elements, wide-function multiplexers, and carry logic3. Digitally Controlled Impedance(D)is available on v/Os of all devices4. I/O standards suppoted HT, L/DS, LVDSEXT, RSDS, BLVDS, ULVDS, LVPECL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVTTL, PC133, PC166, PCI-X, GTL, GTL+, HSTLI (1.2V, 1.5V, 1.8V, HSTLll(1.5V,1.BV), HSTL II (1.5V,1.8v),HSTL IV(1. 5\, 1.8V), SSTL2 1, SSTL2 Il, SSTL18 1, SSTL18 ll5. All Virtex-4 LX and Virtex-4 SX devices available in the same package are foolprnt-compatible6. All products available Pb-free and RoHS-ComplianImportantVerityalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.com/virtex4≤XL|NXXILINX VIRTEX-4 FAMILY FPGAS -2Q20095≤XLNXXILINX VIRTEX- FAMILY FPGAs -2Q20096Virtex-ll Family, Virtex-ll Pro Family FPGAsirtex-ll FamilyVirtex-II Pro FamilyHigh-performance Logic(1.5 VoltHigh-performance Logic with Serial Connectivity (1.5 Volt)Part Number XC2V40 XC2V80 XC2V25C×c%o×co×cy1500×c03×c040c96×c09c0×c4×cP7xce2 o XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100Easy ath"Cost Reduc: ion Solutions (XCE2VP30 XCE2\P40 XCE2VP50 XCE2VP70 XCE2VP100Slices (ay30721c7523,008Logic Resources34566,91211520172804,1922255518407603210438231686,76811,0843,675,448C-B Flip-Flops51221,50428,57246,08093,18627,39238,73447232Maxitlurn Distr ibuleu RAM(Kbis)720Memory Resources Block RAN/FIFO w/ECC (18Kbils each)Tutal Bluck. RAM(Kbis)1,72821e44日7,992Clock ResourcesDigi: al Clock Managers(DCM)Maximum Single-Enced 1/Os6241/0 ReseMaximum Differential I/O Pairs60136436055526:4276372396572-25, LVPECL-33 LVDS-33, LVDS-26, LVDSEXT-33, LVDSEXT-25, BWDS-26, ULVDS-25, LVTTL, WCMOS33, LVCNOS25, L/CMOS18, LVO4OS15, FC133, PCl66, PC-X, GTL, GTL+, LDT-25, L/DS-26, LVDSEXT-25, BLVDS-25, ULVDS-26, -VPECL-25, LWCMOS25, LVCMOSI B, LVCMOS 15, PCI33. LVTTL, LVCNOS33, PCi-X,HSTL, HSTL IL, HSTL I, HSTL IV, SSTL2L, SSTL2IL, SSTL3 L, SSTL3 l, AGP, AGP-21e0Embedded0144010601923110044HErd IPRoclootlo Tranaccivcrs44860120m161600ResourcesPowerPC Processor Blocks0Commercial (slowest to fastest)-4,-5-6-4,-5,-6-,-5,-64,-5,-3-4,-5.-64.-5.-64.-5.-64,-51-6-4,55,-6,-76.75,-6,5,-6,-75,-6,-75.-6.-7Speed GradesConfiguratioConfiguration Memory(Mbits)0.4.8677.521.929.144821135.59.025.65ackeeAvailable User I/OsChip Scale Packages(CS):wire-bond chp-scale BGA(0.0 mm ball spacing)cS144FG79835 x35 mm51617 x mm88FG45623x 23 mm156(494A(494(8)FG676156A34404(8)A16A16(8416(8FFA Peckagcs(FF): flip-chip firc-pitch 3GA(1.0 mm ball spacing)FF67227x27m348(4)FrE9G mm396(0)556(0上115235 x 35 mm824564(8)644(8})392(12)692(16FF114B35 x 35 mmB12(0)x 40 mm912852(14(16)F=169625x425mm1164(0)A2.5x425996(20)104c(20)BFA Pack-chip fine-pitch BGA(1.27 mm ball ep40x40634R84Notes: 1. Easy Path" solutions provide a convers on- free and low-risk path for volume praduction: commerical-grade available on slow and mid speed bins( slow bin orly on largest device) industrial-grade available cn slow speed.3. Digitally Controlled Impedance(DCI) i3 available on I/Oa of all dcvicos4. Available l/O for each devicB-package combination: number of Selectlo pins (number of Rocketlo transceivers)5. All products available Pb-tree and HoHS-ComplImportantVerifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.com/virtex2orwww.xilinx.com/virtex2proSpartan-6 Family FPGAsSPARTANVSpartan-6 LX FPGAsSpartan-6 LXT FPGAsOptim zed for Lowest Cost Logic, DSP, and MemoryOptimized for Low Cost Logic, DSP, and Memory(1.2 Volt, 1.0 Volt)with High Speed Serial Connectivity (1.2 Volt)Part Number XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC5SLX100 XC6SLX150 XC6SLX25T XCESLX45T XCBSLX75TXC6SLX1O0TXC6SLX150TSlices (1)6823038Logic ResourcesLogic Cells ?3,840915214,57924,051436101,2611474432405143,66174637101261147,443CLB Flip-Flops4,E0011440182254576126.5761843043006454576126576184304Maximum Distributed RAM(Kbits79016204162968138203401620615Memory ResourcesBlock RAM(18K bi:s each172116Total Block RAM(Kbte)()2165765762,0880964,3242C884.824Clock ResourcesClock Manager Ties(CMT)(424670I/O ResourcesMaximum Differential Pairs116179200285148160245265DSPABA1 Slices ()1658121010EmbeddedHard IPPCI Express" Endpoint BlockResourcesMemory Controller Locks44GTP LOW-Power Transceivers868CommercialSpeed Grades232.3232323232.32.3h412121241241241241241ConfigurationConfiguration Memory(Mbits)22.719.617.17719.617.1PackageAreaMaximum User I/O: SelectIOM Interface Pins(GTP Transceivers)(?Chip Scale Packages(CPG): Pb-Free wire-band BGA(0.5 mm ball spacing)CPG1968x8 mmTQFP Packages(TQG): Pb-free thin QFP(0.5 mm lead spacing)TQG14420 x 20 mm100Chip Scale Packagce(CSG): Po-froo wiro-bond chip soale BGA(o 8 mm ball pacingCSG 22513x13n15 x 15 mm226218190(4)CSG48419 x 19 mm310330290(4)230(4)2G0(4FGA Packages(FTG): Pb and Pb-free wire-bond fine-pitch thin BGA(1.0 mm ball spacing)FGA Packages(FGG): Fb and Pb-free wire-bond fine-pitch BGA(1.0 mm ball spacing)23 x23 mm296(4)FG(GX27 x 27mm358320(8)396(831x31 mmNotes: 1. Each Spartan-6 FPGA CLB contains four LUTs and eight flip-flops2. Spartan-6 FPGA logic cell ratings refincreased logic capacity offered by the new B-input LUT architecture.3. Block RAMS are fundamentally 18Kb in size. Each olock can also be used as two indeperdent 9Kb blocks.4. Each CMT contains two DCMs and one Pll5. Each DSP48A1 slice contains an 18x18 multiplier, an adder and an accumulator6. Preliminary product information, subject to change. Please contact your Xilinx representative for the atest information.7. Due to the transceivers in the lXt devices, the lx pmouts are not compatible with the lx device pmoutsImportantVerifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.com≤XL|NXXILINX SPARTAN-6 FAMILY FPGAs -2Q20097≤XLNXXILINX SPARTANR SERIES FPGAS-2Q20098Spartan -3A, 3an 3A dSP FPGAsExtended Spartan-3A FarOptimized for Lowest Total CostPart Number XC3S50A/ AN XC3S200A/ AN XC3S400A/ AN XC3S700A/ AN XC3S1400A/ AN XC3SD1800A XC3SD3400ASystem Gates (1)400Kc400KSlices(2)3584112643872Logic Cell9041246543744053,712CLB FIip-Floos1.40835847.168.7763328047744Maximum Distributed RAM(Kbits)Memory Resources Block RAM Blocks (1 8k hits each126Total Block RAM(Kbits)2885761,5122,26Non-VoatileUser Flash(Kbits)(3)-/27/3.054-/2,380/5779-/12.251Clock RcsourccsDigital Clock Managers(DCMs)Maximum Single Erded 1/Os144/1000241511125258112/9016521/O Resources1/0 Standards Supported LTTL UCMOS93, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12 HSTL15 Clace I, HSTL15 Clae IL HSTL18 Claee l, HSTL18 Clae llHSIL18 Class Il, PCl 3. 3V 32/64bt 33MHZ, PCI 3.3v 64bt/66M/Hz, PCcl-x 33V, SsIL3 Class L, SsIL3 Class ll, ss IL2 Class L, ssIL2 Class ll,SSTL18 Class I, SSTL18 Cass l, Bus LVDS. LVDS25&33. LPECL25& 33. Mini-LVDS25&33. RSDS25& 33. TMDS33 PPDS25& 33Embedded HardMultipliers/DSP48A Blocks126(4)IP ResourcesDevice DNA SecuritySpeed Grades454:545Industrial-4.-4L()4.-4L(5ConfigurationConfiguration Memory B ts(Kbits)04248.217Package 6MaxImum User I/OsVQFP Packages(VO): very thin QFP (0.5 mm lead spacing)V10016x16 mm68/-(7)68/-()TQFP Packages(TO): thin aFP(0. 5 mm lcad spacingTQ14422 x 22 mm10B;108FGA Packages(FT): wire band fine ptch thin BCA (1.0 mm ball spacingFT25617 mm144/-(7195/195195/-(7161/-(7)161/-Chip Scale Packages(CS): wire-bond chip-scale BGA (0.8 mm ball spacing)Cs48419 Y 19 mm309(5FGA Packages (FG): wire-bond fine-pitch BGA (1.0 mm ball spacing)9x19 m248/-m7251/FG40021 x 21 mm311/311311/FG48423: 23 (TIr1372/372375FG67627y 27 mm502/50519469Notes: 1. Systcm Gatos includ 20%%-30% of CLBo uCd as RAMs 2. Each clicc comprises two 4-input logic function generators(LUTs), two storagc clements,wide-tunction multiplexers, and carry logIc 3. Sparan-GAN User Flash is the space lett in the on-chip Flash atter a portion Is used to storeuration bitstreamIntegrated in the dSP48A slices(Advanced Multiply Accumulate elemant)5. The L low-power option is exclusively available in CS(G)484 package andIndustrial tcmpcraturo rangc 6. All productc availablc Pb-froo and RoHS-Compliant, chock datashcct for Pb package availabiliy7. Package not available in non-volatile Spartan-3AN familyImportantVerifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.comSpartan-3& 3E FPGAsSpartan-3 FPGASpartan-3E FPGAsOptimized far High Dersity and High I/O DesignsLog c Optim zedPart Number XC3s50 XC3s200 XC3S4C0 XC3S 1000XC3S1500 XC3S2C00 XC3S4000 XC3S5000 XC3S1DCE XC3S25CE XC3S500EXC3S120DEXC3S1600ESystem Gate150oK100K1,920358420,48027,482,44814752Logic Resources80E446.C802.16010.476CLB Flp-Flaps1536384071681536026,62440.6055,29666.51.9204,8969,312734429,504Maximum Distriputec RAM(Kbits)120561202089042520Memory ResourcesBlock RAM Blocks(18k bits each)16Total Block RAM(Kbits)721628425767x07281872216Clock ResourcesDigital Clock Managers (DCMs)4444Maximum Single Enced/Os124173633Maximum D fferential I'O Pairs00O ResourcesLVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, GTLGTL, HS L15 Clase I, HSTL15 Clace L, HSTL1 8TTL LVCMOS33, VC12 HSTL18 Clace I1/O Standards Supported class l HSTL13 Class l, HSTL 18 Class ll, PC 3. 3v 32/64bit 33MHz SSTL2 ClassI, SSTL2 Class ll SSTL18 Cass l, Bus LVESHSTL18 Class lll, PCI 3.3Y 32/64Eit 33MHz, PC133V 64CHX 33V, SSTL2LDT(ULVDS), LVDS exl, LYDS25 & 33, L/PECL25, RSDS25Class I, SSTL1B Class L BJs LVDS. LVDS25, L/PECL25RSDS25Embedded Hard IP ResourcesCommercialSpeed Grades44546445464464646464546industial44ConfigurationConfigurat on Memory BitE(Mbite0.43.213.31.43.86.CPackage. 31AreMaximum User l/osVOFP Packages (VQ): vary thin QFP (0.5 mm lead spacing)VArcO15 x 16 mmChi Scale Packages(CP): wire-bond chip-scale BGA(0. 5 mm ball spac ng)CF1328 mmTOFP Packages (TO) thin OFP (0.5 mm lead spacing)1Q14422 22 mmPOFP Packages(PO: wire-bond plastic QFP (0. 5 mm lead spacing)PG208FGA Packages(FT): wire-bord fine-pitch thin BGA (1.0 mm ball spacing)FT25617x117172FGA Packages(FG): wire-bond chip-scale BGA(1. C mm bail spacingG320221222E0=G40021 x 21 mmFG45623 x23 mmFG48423 x 23 mmFG67627 x 27 mm489FG90031 x31 mminclude 20%-30%o of CLBs used as RAMs. 2. Each slice comprises two 4-input logic functor generators(LUTs), two storage elements, wide-function multiplexers, and carry logic3. All products available rb-free and RoHS-Compliant. 4. Available only in vQG100 package vQG 100 and vQ100 have identica pinoutsImportantVerifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.com≤XL|NXXILINX SPARTANR SERIES FPGAS-2Q2009≤XLNXXILINX CPLD PRODUCTS-2Q2009Product selection Matrix- CoolRunnerm seriesCoolRunner-l FamilyCoolRunner XPLA3 FamilyPart Number XC2C32A XC2C64A XC2C128XC2C25XC2C384 XC2C512 XCR3032XL XCR3064XL XCR3128XLXCR3256XLXCR3384XLXCR3512XLSystem Gates7501.5006,0009,0001.5006,000Logic ResourcesMacrocells1283851284512Product terms per Macrocell6565666866484Global GlocksClock ResourcesProduct Term Clocks per Function Block16161661616152701/0 ResourcesInput Voltage Compatible15/1.825/3315/18/25/331518/253315/8/253315/8/25/3315/825/33.3/33/53.3/53./5Output Voltage Compatible15:825/315618/25/3151253315/18/25331518253315/1825/333333Min. pin-to"pin Logic Delay (ns)4.657.17.1beeaCommerc al Speed Grades( Fastest to Slowest5,-7,-10-7,-10,-12,10,12Industrial Speed Grades(Fastest to Slowest-677710-7.1107.-100.-121C,-1210,-12Maximum User l/OsQFN Packages(OFG): quad flat no-lead ( C 5 mm lead spacing)QF32)5x5VaFP Packages(/C): very thin QFP (VQ44: 0.8 mm lead spacing, VQ100: 0. 5 mm lead spacing)Xilinx CPLDs provide the flexibilityVO442x 12 mm16 mmto add innovation to your applicationChip Scalc Packages(CS): wirc-bond oniF-sDalc BGA(0.8 mm ball spacing)while maintaining the fastest timeCS487x7 mmto- markets142x 12 mm108Offer low power, low cost, and small formfactor benefits all in one device6x 6mmCP1328100106Free reference designs and /P shortenTQFP Packages (TO): thin QFP(0. 5 mm lead spacing)design cyclesTQ10016x 16 mm120118022 x 22 mm100118118Industry's widest density and package selectionPOFP Packages(PQ): wire-bond plastic OFP (O 5 mm lead spacing)PO26x.6 mm173164172180FGA Packages(FT): wire-bond tie pitch thin BGA (1.0 mm ball spacing)FBGA Packages(FG): wire-bond fine-line BGA(1.0 mm ball spacing)FG32423 x 23 mmavailable in FT(G)256 package. 2 All packages availableons for lead-frame product are inclusive of the leads4. Only available in RoHS6 compliant and Halogen-free packages. 5. JTAG pins and port enable are notnpat ble in this package for this member of the familyImportantVerityalldatainthisdocumentwiththedevicedatasheetsfoundatwww.xilinx.com