NXP Cortex M3 MCU

NXP Cortex-M3 32BIT MCUNXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontrollerCAn controller with two channels■ Digital peripheralsSD/MMC memory card interfaceo Up to 165 General Purpose l/0(GPlO)pins depending on the packaging, withconfigurable pull-up/down resistors, open-drain mode, and repeater mode. AllGPlOs are located on an ahb bus for fast access and support cortex-M3bit-banding. GPlOs can be accessed by the general Purpose DMA Controller. Anypin of ports 0 and 2 can be used to generate an interrupto Two external interrupt inputs configurable as edge/level sensitive. All pins on port Oand port 2 can be used as edge sensitive interrupt sourcese Four general purpose timers/coith a total of eight capture inputs and tencompare outputs. Each timer block has an external count input. Specific timerevents can be selected to generate dMa requestse Quadrature encoder interface that can monitor one external quadrature encodero Two standard PWM/timer blocks with external count input optiono One motor control PWM with support for three-phase motor controlQ Real-Time Clock(RTC)with a separate power domain the RtC is clocked by adedicated RTC oscillator. The RtC block includes 20 bytes of battery-poweredbackup registers, allowing system status to be stored when the rest of the chip ispowered off. Battery power can be supplied from a standard 3 V lithium button cellThe rtC will continue working when the battery voltage drops to as low as 2.1An rtc interrupt can wake up the CPu from any reduced power modeo Event Recorder that can capture the clock value when an event occurs on any ofthree inputs. The event identification and the time it occurred are stored inregisters. The Event Recorder is located in the rtc power domain and cantherefore operate as long as there is rtC powerWindowed Watchdog Timer(WWDT). Windowed operation, dedicated internaloscillator, watchdog warning interrupt, and safety featuresCRC Engine block can calculate a CRC on supplied data using one of threestandard polynomials. The CRC engine can be used in conjunction with the DMAcontroller to generate a CRC without CPU involvement in the data transferAnalog peripherals9 12-bit Analog-to Digital Converter(ADC)with input multiplexing among eight pinsconversion rates up to 400 kHz, and multiple result registers the 12-bit Adc canbe used with the gpdma controllerQ 10-bit Digital-to-Analog Converter(DAC)with dedicated conversion timer and DMAsupport■ Power controFour reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-downThe Wake-up Interrupt Controller(WiC)allows the cpu to automatically wake upfrom any priority interrupt that can occur while the clocks are stopped inDeep-sleep, Power-down, and Deep power-down modeso Processor wake-up from Power-down mode via any interrupt able to operateduring Power-down mode(includes external interrupts, RTC interrupt, PORTO/2pin interrupt, and NMi)Brownout detect with separate threshold for interrupt and forced resetQ On-chip Power-On Reset(POR)LPC178xAll information provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reserObjective data sheetRev.2-27May201130f117NXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontroller■ Clock generation:o Clock output function that can reflect the main oscillator clock, IRC clock, RTCclock, CPU clock, USB clock, or the watchdog timer clockQ On-chip crystal oscillator with an operating range of 1 MHz to 25 MHzQ 12 MHz Internal RC oscillator(IRC)trimmed to 1% accuracy that can optionally beused as a system clockQ An on-chip PLL allows CPU operation up to the maximum CPU rate without theneed for a high-frequency crystal. may be run from the main oscillator or theinternal rc oscillatorO A second, dedicated PLL may be used for USB interfader to allow addedflexibility for the Main PlL settingsa Versatile pin function selection feature allows many possibilities for using on-chipperipheraUnique device serial number for identification purposesa Single 3. 3V power supply (2. 4v to 3.6V) Temperature range of-40C to 85CAvailable as lQFP208, TFBGA208, TFBGA180, and LQFP 144 package3. Applications■ Communications:o Point-of-sale terminals, Web servers, multi-protocol bridges■| industria| Medical!o Automation controllers, application control, robotics control, HVAC, PLC, inverterscircuit breakers, medical scanning, security monitoring, motor drive, video intercom■ Consumer/ AppliAudio, MP3 decoders, alarm systems displays printers scanners smallappliances, fitness equipmentAutomotiveAfter-market, car alarms, GPS/fleet monitorsLPC178xAll inform ation provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reserObjective data sheetRev.2-27May201140f117NXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontroller4. Ordering informationTable 1. Ordering informationype numberPackageNameDescriptionVersionLPC1788LPC1788FBD208 LQFP208 plastic low profile quad flat package: 208 leads; body 28 x 28 x 1.4 mm SoT459-1LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package: 208 balls; bodysOT950-115×15×0.7LPC1788FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls, body 12 x 12 x 0.8 mm SOT570-2LPC1788FBD144 LQFP144 plastic low profile quad flat package; 144 leads body 20 x 20 x 1.4 mm SOT486-1LPC1787LPC1787FBD208 LQFP208 plastic low profile quad flat package: 208 leads; body 28 x 28 x 1.4 mm SOT459-1LPC1786LPC1786FBD208 LQFP208 plastic low profile quad flat package 208 leads; body 28 x 28 x 1.4 mm SOT459-1LPC1785LPC1785FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1LPC1778LPC1778FBD208 LQFP208 plastic low profile quad flat package: 208 leads; body 28 x 28 x 1.4 mm SOT459-1LPC1778FET208 TFBGA208 plastic thin fine-pitch ball grid array package: 208 balls; bodySOT950-115×15×0.7mmLPC1778FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls, body 12 x 12 x0.8 mm SOT570-2LPC1778FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1LPC1777LPC1777FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1. 4 mm SOT459-1LPC1776LPC1776FBD208 LQFP208 plastic low profile quad flat package: 208 leads; body 28 x 28 x 1.4 mm SOT459-1LPC1776FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 x 12 0.8 mm SOT570-2LPC1774LPC1774FBD208 LQFP208 plastic low profile quad flat package: 208 leads; body 28 x 28 x 1.4 mm SOT459-1LPC1774FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1LPC178xAll inform ation provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reserObjective data sheetRev.2-27May20115of117NXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontrollerTable 2. LPC178x/7x ordering optionsAll parts include two CAN channels, three SSP interfaces, three /2C interfaces, one/2S interface, DAC, and an 8-channel12-bit ADCType number Flash CPU Peripheral Total EEPROM Ethernet USB UART EMC LCD QEI SD/B) SRAM SRAM SRAM(byte)MMC(kB) (kB)(kB)LPC178xLPc1788FBD208/5126416×2032H/O/D 532-bitYY YLPC 1788FET208LPC1788FET1805126416×24032YYYNYNH/O/D 516-bit YY yLPc1788FBD1445126416×24032H/O/D 58-bit YY yLPC1787FBD20851216×29604032H/O/D 532-bitYY YLPc1786FBD2082566416032H/O/D 532-bit YY YLPc1785FBD20825616804032H/O/D 532-bit yPC177XLPC1778FBD208′5126416×2964032YH/O/D 532-bit n yLPC 1778FET208LPC1778FET1805126416×2964032H/O/D 516-bit Ny yLPC1778FBD1445126416×2964032H/O/D 58-bit ny yLPC1777FBD208512616×24032LPC1776FBD20825664164032YNYYNNH/O/D 532-bit NY yH/O/D 532-bit Ny yLPC1776FET18025664164032H/O/D 516-bit NY YLPC1774FBD208128328402016D532-bit nN NLPC1774FBD1441283282016D42 NNN[Maximum data bus width of the External Memory Controller(EMC )depends on package size. Smaller widths may be used2 USART 4 not availableLPC178xAll inform ation provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reserObjective data sheetRev.2-27May20116of117NXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontroller5. Block diagramdebugJTAGportLPC 178x/7xTEST/DEBUGINTERFACECLOCKGENERATIONCORTEX-M3CoNTROLLER ETHERNET(1)ARMGPDMAUSBSYSTEMDEVICE/HOST()OTG(1)FUNCTIONSclocks and-code D-code systemmastermastemastercontrolsbusslaveslaveEMCROMSlaveLCD(1)MULTILAYER AHB MATRIXslaveslaveslaveHIGH-SPEEDGPIOCRCAHB TO AHB T(FLASHACCELERATOR4032BBRIDGE0BRIDGE2016BFLASHAPB slave group OEEPROM512/256/12864kBSSP1APB slave group 1UART0/SSP0/2UART2/312c0USART4(1)CAN OR12c2TIMER 0/1SD/MMc(1)WINDOWED WDTTIMER2/3PWM0/12-bit ADCQUADRATURE ENCODER(1)PIN CONNECTDACGPIO INTERRUPT CONTROLEVENT RECORDERMOTOR CONTROL/。32kHzSYSTEM CONTROLOSCILLATORRTCBACKUP REGISTERSRTC POWER DOMAIN Iconnected to gpda002aa5281)Not available on all parts. See Table 2Fig 1. Block diagramLPC 178x7XAll inform ation provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reservObjective data sheetRev.2-27May201170f117NXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontroller6. Pinning information6.1 PinningLPC178x7xFBD208002a518Fig 2. Pin configuration(LQFP208index area2468101214161357911131517AOOOOOO0O000000000B| OOOOOOOO。oo。ooooC00000000000000000o000000000 MODOCE|。ooOOooFO0OOHonOOdooOLPC178x7x 00O0KOnOLOgONOOOOP00000000000000000R0OOOO0O00O0OOOOOOT00000000000000000U 00000000o。 OOOOOOTransparent top viewFig 3. Pin configuration (TFBGA208All inform ation provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reserObjective data sheetRev.2-27May20118of117NXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontrollerball a1LPC178x/7xindex area1234567891011121314BLOOOOOOOOOOOOOCFoo○○○OOOCJo○NO000O00O0OOOOOTransparent top viewFig 4. Pin configuration(TFBGA180LPC178x/7XFig 5. Pin configuration (LQFP144)6.2 Pin description10 pins on the LPC178x/7x are 5v tolerant and have input hysteresis unless otherwiseindicated in the table below. Crystal pins, power pins, and reference voltage pins are not5V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5Vtolerant and the input voltage must be limited to the voltage at the adc positive referencepin(VREFP)All port pins Pn[m] are multiplexed, and the functions appear in their order defined in theFUNC bits of the corresponding locon register. Each port pin can support up to eightmultiplexed functions. IoCoN register FUNC values which are reserved are noted as"Rin the pin configuration tableLPC178xAll inform ation provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reserObjective data sheetRev.2-27May201190f117NXP SemiconductorsLPC178X/7x32-bit ARM Cortex-M3 microcontrollerTable 3. Pin descriptionNot all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEL, SD/MMC, DAC pins) and Table 7(EMCpins)SymbolDescriptionmL=三Po[D]to1/0 Port 0: Port 0 is a 32-bit l/O port with individual directionP0[31controls for each bit. The operation of port 0 pins depends uponthe pin function selected via the pin connect blockPo[O]94 U15 M10 66 3] I; 1/0 P0[0]-General purpose digital input/output pinPU CAN_RD1-CAN1 receiver inputo U3 TXD- Transmitter output for UaRT31/0 12C1_SDA-12C1 data input/output(this pin does not use aspecialized 12C pad)10 U0_TXD-Transmitter output for UARTOPo[196 T14 N11 67 3 I; l0 Po[1]-General purpose digital input/output pinPUo CAN TD1- CaN1 transmitter outputU3 RXD- Receiver input for UART310 12C1 SCL-12C1 clock input/output( this pin does not use aspecialized 12C padI U0_ RXD-Receiver input for UARTOPO202 C4 D5 141 3] I; 1/0 P0[2]-General purpose digital input/output pinP∪OU0 TXD- Transmitter output for UARTOo U3_TXD-Transmitter output for UART3PO204D6A3142; 10 Po[]-General purpose digital input/output pinPUU0 RXD- Receiver input for UArtoI U3 RXD- Receiver input for Uart3P04168 B12 A11 116 3 I; /0 P0[4]-General purpose digital input/output pinPU VO 12S_RX_SCK-[2S Receive clock. It is driven by the masterand received by the slave. Corresponds to the signal SCK in the/2S-bCAN RD2-CAN2 receiver inputT2 CAPO-Capture input for Timer 2, channel 0R-Function reservedR— function reservedR-Function reservedo LCD VD[O]-LCD dataLPC178xAll inform ation provided in this document is subject to legal disclaimersE NXP B V. 2011. All rights reserObjective data sheetRev.2-27May201110of117