联想y470图纸

维修图纸联想y470 独立显卡图纸 完整版本 用pdf打开TALSTATELP_S1* SLP_$3# SLP_54#SLP_S5#+VALN+VsClockVoltage RailsFul ONHIGHHIGH HIGHHIGHSI(P。 wer On SuspendHIGHHIGHFLIGH工OS3 (Suspend to RAM)LOWI GHHIGHOFEOF'R+5VSs4 (Suspend to Disk)工oWH工GHOFF+3VSpowerlane+1. 5vss5(s。fOFF)OFF+5VALn1.5V+CPU COREtVGA CoREBoard id/ sKU ID Table for ad channelt sVALn+1. avSRa/Rc/Rel 100K +/-54state+0.75VsRbRd/ rEALB工DVAD BID typVAD BID max+1.05vs2K+/-5各16V0.250V0.289V18K5号0.436V5030.538V33K0.712V0.819v0.875V56K+/-5号1.185V1.264V100K+/-51.453V1.650Vs200K+/-5影1.935V2.200V2.341V2.500V3.300v3.300VS3BOARD D TableBOM Structure TableBro ItemBoMS七 uctureS5 S4/AC●Board工DPCB RevisionUMA0.1s5 s4/ Battery onlyUMA。n1yUMA ONLY@xOPT工S5 S4/AC Batterydon t exist匚xxxxHDM工HDM工aB1ue。othSMBUS Control tableUSB30@ThermalSOURCE VGA BATT KB930 SODIMM WLAN SensorPCHUSB ChargerUSB CEG@WWANNo USB ChargerNO CHG@SMB EC DAI KBAW XUSB Port TableUnpopCodec Alc272+3VALWExternalMB EC CK2USB 2 o USB 1.lPortUsBP。rtCodec lc55035503aAN5778157781SMB_EC_DA2 +3VALWXXXXXXUHCIOUSB/ Cable(Right Side)IAN57780SMBCLKXⅩXX X1 USB Port( Right Side COMBq)577808XXXVentura FeatureVENTURAGSMBDATA+3VALW+3VSSMLOCL工1UHCI2 USB/B(Left Side)CameraEHCI1USB/B ( Left Side)SMLODATAUHC工2SML1CLKPCHXXCameraSMLIDATAVRAM BOM ConfigUHc工X761GQ: X7625738L01 Samsung 1GBSub: X7625738L02 Hynix 1GBUHC工4X762G@: X7625738L03 Samsung 2GBEC SM Bus1 addressEC SM Bus2 addressMini Card( WLANSub: X7625738 L04 Hynix 2GBDeviceEHCI2UHCI 5AoAddressGPU BOM ConfigSmart Batteryc001011XbThermal sensor FMC 141)3-21001101b12N12P SKUOPTIaUHCI 613Blue ToothGS SKUGSOGT SKUGTOPCH SM Bus addressDeviceAddressCDR DIMMOSecurity ClassHlcatlonCompal Secret DataCompal Electronics, IncDDR DIMM2100 LxbDeciphered DateNotes List千 T OF ENGNFF&DPIQYO LA6881PUSED BY OR DISCLOSEDaednesday January 05, 20-3VS VGAIVCA CORE+1.8VD30IL. 5VS VCASecret DataCompal electronics. Inc.Deciphered CateAF COMPA FIFCTRONICS INC AND COMTAINS OFIN FNTIAIVGA Notes listPIQYO LA6881PAnGRy n5. 2011PEG ICOMPI and RCOMPO signals should besorted and routedwith-max length 500 mils -typicalimpedance= 43 mohmsPEG ICOMPO signals should be routed with./length 500 mils24904021%typical impedance 14.5 mohmsDMI_R>+[OTP三oRcPCIE_CRX_ GTXNO 15]<23<15> DMI CRK PTXPE3 Rxa! IM3EG static lane Reversal- ceG2 is for the 16x<15PEa REaL2 MI CTX PRX NORNormal operation: Lane def-nition matcescket pin map definition135》N<18> DMI CTX PRX N3DMTX群3口: ane Rever seCTX PRX F「PRX_G1XH0.1<3PEG RADI35←15> FDI CTX PRH<15 FDI GTX PRX NCTX PRX PDPES RX11SI B32FCIE CTX GFX NJO.. 15] <23>rC1s FCI CTX PRX PT[+1.CvsFDSYNCIFDIO - SYNICDIl-SYNCSYNCO6> FD LSYNCO下 DI LSNCU PEG- TXi EFDIl LSNEDP COMPPFGeDP COMPIo and ICOMPo signalsCT> GFX C P15PCIE CTX GRX P1FCIE_CTX_ GRX_P0.15] 423>should be tied together, thenUDP HPDPEG TXI HMconnected to the vccio raila singlc 24. 9ohm resistorH81VKcE我RF①Scourity ClassificationCompal secret DataCompal electronics, Incsucd DatcDeciphered DatePROCESSOR(/7)DML FDI PEGEON OF R&DcanBy oe msdos。RONICS, INC.Date: WednesdayShoat 5 of 63R10004025%DG1.0CLK CPU DMI <15PROG SELECTHI RI1 J ALK CPU DMH HPEc<1H PECI IsOPECHo一> H DRAMEST"5%45> H PROCHOTE#□H PROCHOT+DDR3 Compensation signalsC_04025》613> H IHHM I HIPt H PM SYNC2 H PM SYNC R AM34_SYNCIgnals<19>H_CPUPWRGDPwRGD HPM DRAIA PWRGD 3CBR# bALis XD-DBRES11K040250+sBPM*oIA226 XDP BPRESETBPM*]IPGA_ Rev1p3VALAuffered reset to CPU+3v10K0C25%a o pw sYs FuRGD BUF<16> PM_DRAM_PWRGD75C4025%4AHCIGOCGW TSSOPERIlF CPI ASTa2的43D4025PLT RSSN7ALVC1G07DCKF SC70-6PLTR8T#←18<1051:7>5J3°□Scourity ClassificationCompal secret DataCompal Electronics. Isucd DatcDeciphered DatePROCESSOR(2/7 PM,XDP, CLKReycanBy oe msdos。A688PRONICS, INC.Date: WednesdayShoatCPiSA CLKEB MaLK DORO 1 2, c13> DDR E DIC B312O2H0∽α→ DDR_E DCS0.7138_D0St0JSB MAOI2> DcF-A BS3:BB1SA MAITSDDR uAL13> DDA R CASB CAS址8B42A348-A394 SB_WEAFAS+&. NE#3是0 [PGA Rev1 p0Sardy Brldge rFGA Re/10004n≥5%心6 H DRAMRSTH[>DDR3 DRAMRST#日CDRS5oDRAMRST_CNTRL_FCHDMDRAMRS CNTRLEiffel used 0, 01vSecurIty classificationCompal Secret DataCompal electronics, InU0402164Module design used 0.047Deciphered DatePROCESSOR(3/7)DDRIITHIS SHEET NORTH INEDRMATEON TICCNTANSMAY BE USED BY OR DISCLO3ED TO ANY THIFD PAFTY WIITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.PIQYD LA688IPWednesday, January 05, 2011CFG straps for processorCH2R41iK04021%PEG static Lane Reversal- CFG2 is for the 16x1: Normal CperatiLane t definition matcheston★0: Lane ReversedFSVD35I Display Port Presence Strapmyrica⊥ DisplaC=4G VAL SENSE器attached tc Embedded D:splay PortcUnllecLed Lo Lie Embedde: Displdy Pcrc evice is0: Enabled; An external Display Port device isFSVma∽GFSVD461FEVD6②F43d231FSVD8tK04021%FSVC13VCC DIE SENSEPAD T13PCIE Port Bifurcation Straps*11:(Defa:llt)x16- Device 1 functions 1 and 2 disabiedSV023ion 1ASVD601: Roccrvcd-(Dcvicc 1 function 1 d=cabled i funct:onCIO SELea⊥e(:×8,x4,×4- DeVICe1 Fictions1 and 2 enabledJ15 FSVD2KEYC7eA39∈ reno0: PEG Wait for BIos for trainingScourity ClassificationCompal secret DataCompal electronics, Incsucd DatcDeciphered DatePROCESSOR(4/ RSVD, CFGEON OF R&DcanBy oe msdos。RONICS, INC.Date: WednesdayShoatPOWERCPU CORECap quantity follow HR_ PDDG_ Revo6/16 change10uF06036.3V)*5QC=94A22uF 7 NO STUFF18ALCGVSDC=534(22uE08056.3V)*13C上坠上8上腿8上8⊥8⊥88Ncg品a2gNNCg8oCPU GOREA八1130040256。:105Vs330uF)*48/11 update: Add R1309, R1310PDDG1.21#439028DUALIC DUAL@DUAL②4021%器资是最是VCCSFNSF FO>+105V8H1313“822R92W209waLICCIO SENSE0m匚> VCCI SENVGGIO SENSE21004021%P261 NCCsBs° PCa SedRrity ClassificationCompal secret DataCompal electronics, Incsucd DatcDeciphered DatePROCESSOR(5/7)PWR, BYPASSReycanBy oe msdos。A688PRONICS, INC.Date: WednesdaySnot 9 of 6311/17 35 change to 20KEN4240_040210veKsorer10KC4025%DMN303OLSS-13 SOP8L-8r45> CP 5U S3 GATF30kK04025%c1U0603257MPOWERGFX CORECPUTGA124 AXG1E影坚斗閏+159 CPU NDDo图2F息6719A8RE1SM VREFV SM VREF CNT301GN-HF_SOT23.3〉R63E8上AMAAAAxAvAXG2+' 5V CPU VDDO8--8/123stuff defaultDDOSceg+CCSA5ancy eridge卜 GAHev'p望多品1.5A+1.3Vs YCCPLLVCCEA SENSEVCCSA SENSE6/9 change 330U t 22t X2Scourity ClassificationCompal secret Datasucd DatcDeciphered DatePROCESSOR(O/7)PWRcanBy oe msdos。A688PRONICS, INC.Date: WednesdayShoat