stm32f407 参考手册

stm32f407 参考手册，里面包含每个寄存器的定义RM0090ContentsPower control (PWR)634.1 Power supplies634.1.1 Independent A/d converter supply and reference voltage644.1.2 Battery backup domain654.1.3oltage regulator4.2 Power supply super684.2.1 Power-on reset (POR)/power-down reset(PDR)684.2.2 Brownout reset (BOR)684.2.3 Programmable voltage detector(PVD694.3 Low-power modes......704.3.1 Slowing down system clocks.....704.3.2 Peripheral clock gating4.3.3 Sleep4.3.4 Stop mode724.3.5 Standby mode734.3.6 Programming the rtC alternate functions to wake up the device fromthe Stop and Standby modes754. 4 Power control registers784.4.1 PWR power control register(PWR CR)784.4.2 PWR power control/status register(PWR_ CSR)794. 4. 3 PWR regist81Reset and clock control (RCc)825.1 Reset825.1.1 System reset翻1面825.1.2 Power reset5.1.3 Backup domain reset845.2 Clocks845.2.1 HSE clock865.2.2 HSI clock5.2.3 PLL configuration885.2.4 LSE clock885.2.5 LSI clock895.2.6 System clock(SYSCLK) selection895.2.7 Clockty system(CsS)895.2.8 RTC/AWU clock905.2.9 Watchdog clock90DoC ID 018909 Rev 13/1316ContentsRM00905.2.10 Clock-out capability5.2.11 Internal/external clock measurement using tiM5/TiM115.3 RCC registers935.3.1 RCc clock control register(RCC_ CR).935.3.2 RCC PLL configuration register(RCC-PLLCFGr)955.3.3 RCC clock configuration register(RCC_CFGR)5.3.4 RCC clock interrupt register(RCC_CIR)5.3.5 RCC AHB 1 peripheral reset register(RCC_ AHB1 RSTR)1025.3.6 RCC AHB2 peripheral reset register(RCC_AHB2RSTR).,,.1045.3.7 RCC AHB3 peripheral reset register(RCC_ AHB3RSTR),,,.1055.3.8 RCC APB1 peripheral reset register(RCC APB1RSTR).1055.3. 9 RCC APB2 peripheral reset register(RCC- APB2RSTR).1085.3.10 RCC AHB1 peripheral clock register(RCC_AHB1ENR),,,,.,1105.3.11 RCC AHB2 peripheral clock enable register(RCC_AHB2ENR)1125.3.12 RCC AHB3 peripheral clock enable register(RCC AHB3ENr)...1135.3.13 RCC APB1 peripheral clock enable register(RCC_APB1ENR)...1135.3. 14 RCC APB2 peripheral clock enable register(RCC_APB2ENR)... 1175.3.15 RCC AHB1 peripheral clock enable in low power mode register(RCC_AHB1 LPENR,,.1195.3.16 RCC AHB2 peripheral clock enable in low power mode register(RCC_AHB2LPENR),..125.3.17 RCC AHB3 peripheral clock enable in low power mode register(RCC_AHB3LPENR1225.3.18 RCC APB1 peripheral clock enable in low power mode register(RCC_APB1LPENR)翻1235.3.19 RCC APB2 peripheral clock enabled in low power mode register(RCC_APB2LPENR)1265.3. 20 RCC Backup domain control register(RCC_BDCR),,,,,,1285.3.21 Rcc clock control status register(RCC CSR1295.3.22 RCC spread spectrum clock generation register(RCC- SSCGR)1315.3.23 RCC PLLI2S configuration register(RCC- PLLl2SCFGR)..... 1325.3.24 RCC register map.134General-purpose Os(GPIO)1366.1 GPO introduction,,,,,,,,1366.2 GPIO main features1366.3 GPlO functional description1366.3.1 General-purpose I/O (GPIO)1384/1316DOC ID 018909 Rev 1RM0090Contents6.3.1/0 pin multiplexer and mapping.1396.3. 3 10 port control registers1416.3.4 10 port data registers146.3.5 0 data bitwise handling,,,,,,1426.3.6 GPIO locking mechanism1426.3.7 l0 alternate function input/output翻D1426.3.8 EXternal interrupt/wakeup lines1436.3.9 Input configuration1436.3.10 Output configuration.1446.3.11 Alternate function configuration1446.3.12 Analog configuration1456.3. 13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15port pins1466.3. 14 Using the OSC_IN/OSC_OUT pins as GPIO PHO/PH1 port pins .. 1466.3.15 Selection of rtc afl and rtc af2 alternate functions....1466.4 GPIO registers1486. 4.1 GPIO port mode register(GPIOx_MODER)(X=A.I)1486.4.2 GPlo port output type register (GPIOX_OTYPEr)(X=A. 1)....1486.4.3 GPIO port output speed register(GPIOX_OSPEEDR(x=A.1496.4.4 GPIO port pull-up/pull-down register (GPIOX_PUPDR)(X=A.)1496.4.5 GPIO port input data register(GPIOX_IDR)(x=A.l),,.1506.4.6 GPIO port output data register (GPIOX_ODR )(X=A. 1).....1506.4.7 GPlO port bit set/reset register(GPIOX_ BSRR)(x=A.D)1506.4.8 GPIO port configuration lock register(GPIOX_LCKR)X=A. I)6.4.9 GPlO alternate function low register(GPlOx_AFRL)(x=A. 1)... 1526.4.10 GPIo alternate function high register(GPIOX_ AFRH)(x=A.)1536.4.11 GPlO register map...1537System configuration controller (SYSCFG)1557.1 1/0 compensation cell1557.2 SYSCFG registers1557.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP).....1557.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMc). 1567.2.3 SYSCFG external interrupt configuration register 1(SYSCFG_EXTICR1156DoC ID 018909 Rev 15/1316ContentsRM00907.2. 4 SYSCFG external interrupt configuration register 2(SYSCFG_EXTICR2...1577.2.5 SYSCFG external interrupt configuration register 3(SYSCFG_EXTICR31577.2.6 SYSCFG external interrupt configuration register 4(SYSCFG_EXTICR4.1587.2.7 Compensation cell control register(SYSCFG- CMPCr)1587.2.8 SYSCFG register maps159DMA controller(DMA)1608. 1 DMa introduction,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,1608.2 DMA main features1618.3 DMA functional description,,,,,,,,,,,,,,,,,,,,,,,,,,1628.3.1 General description1628.3.2 DMa transactions1638.3.3 Channel selection1648.3.4 Arbite1658.3.5 DMA streams1658. 3.6 Source destination and transfer modes1668.3.7Pointer incrementation1698. 3. 8 Circular mode1708.3.9 Double buffer mode1708.3.10 Programmable data width, packing/unpacking, endianess8.3.11 Single and burst transters.1738.3.12FFO1738.3.13 DMa transfer completion1768.3.14 DMA transfer suspension1778. 3.15 Flow controller1778.3. 16 Summary of the possible DMA configurations1788.3.17 Stream configuration procedure1798.3.18 Error management..1808.4 DMA interrupts1818.5 DMA registers188.5.1 DMA low interrupt status register(DMA LISR)1818.5.2 DMA high interrupt status register(DMA_HISR)1828.5.3 DMA low interrupt flag clear register(DMA_LIFCR).,.1838.5.4 DMA high interrupt flag clear register (DMA_HIFCR)1846/1316DOC ID 018909 Rev 1RM0090Contents8.5.5 DMA stream x configuration register (DMA_SXCR)(X=0.7).1858.5.6 DMA stream x number of data register(DMA_ SXNDTR)(X=0.7).1888.5.7 DMA stream x peripheral address register(DMA_SXPAR)(x=0.7). 1888.5.8 DMA stream x memory 0 address register(DMA_SXMOAR)(x=0.7)1888.5. 9 DMA stream x memory 1 address register(DMA SXM1AR)(x=0.7)1898.5. 10 DMA stream x FIFO control register(DMA_ SxFCR)(x=0.7)1908.5.11 DMA register map191Interrupts and events1959.1 Nested vectored interrupt controller(NVIC)1959.1.1 NVIC features,,1959.1.2 Sys Tick calibration value register..1959.1.3 Interrupt and exception vectors1959.2 EXternal interrupt/event controller (EXTI)1999.2.1EXTI main features1999.2.2 EXTI block diagram..1999.2.3 Wakeup event management2009.2.4 Functional description2009.2.5 External interrupt/event line mapping....2019.3EXTI registers2039.3.1 Interrupt mask register(EXTI_IMR)2039.3.2 Event mask register (EXTI_Emr)2039.3. 3 Rising trigger selection register(EXTI_RTSR)...,.2049.3.4 Falling trigger selection register (EXTI_ FTSR)2049.3. 5 Software interrupt event register (EXTI_ SWIEr)2059.3.6 Pending register(EXTI_ PR.2059.3.7 EXTI register map20610Analog-to-digital converter(ADc)20710.1 ADC introduction,,,,,,,,,,,,,,,,,,,,,,,,,20710.2 ADC main features20710.3 ADC functional description20710.3.1 ADC on-off control20910.3.2ADcc|ock,,,,,翻面面,,,,,,20910.3.3 Channel selection20910.3.4 Single conversion mode10.3.5 Continuous conversion mode.210DoC ID 018909 Rev 17/1316ContentsRM009010.3.6 Timing diagram....21110.3.7 Analog watchdog21110.3. 8 Scan mode21210.3. 9 Injected channel management,,,,21210.3.10 Discontinuous mode,21310.4 Data alignment21410.5 Channel-wise programmable sampling time21510.6 Conversion on external trigger and trigger polarity....21610.7 Fast conversion mode21710.8 Data management21810.8.Using the dma..21810.8.2 Managing a sequence of conversions without using the DMA..21810.8.3 Conversions without dma and without overrun detection..21810.9 Multi ADC mode,,,,,21910.9Injected simultaneous mode,,,.,,22210.9.2 Regular simultaneous mode.,,22310.9.3 Interleaved mode22510.9.4 Alternate trigger mode22610.9.5 Combined regular/injected simultaneous mode.22810.9.6 Combined regular simultaneous alternate trigger mode22810.10 Temperature sensor22910.11 Battery charge monitoring23010.12 ADC interrupts23110.13 ADC registers23210.13. 1 ADC status register(ADC_SR23210.13.2 ADC control register 1(ADC_ CR1)23310.13. 3 ADC control register 2(ADC_CR2).23510.13.4 ADC sample time register 1(ADC SMPR1).23810.13.5 ADC sample time register 2(ADC SMPR2)..23810.13.6 ADC injected channel data offset register x(ADC_JOF Rx)(x=1.4). 23910.13.7 ADC watchdog higher threshold register(ADC_HTR)23910. 13.8 ADC watchdog lower threshold register(ADC_LTR).23910.13. 9 ADC regular sequence register 1(ADC_SQR1)24010.13 10 ADC regular sequence register 2(ADC_ SQR2)24010.13 11 ADC regular sequence register 3(ADC_SQR3)24110.13.12 ADC injected sequence register(ADC_ JSQR)8/1316DOC ID 018909 Rev 1RM0090Contents10.13 13 ADC injected data register X(ADC_JDRX)(x=1.4)24210.13. 14 ADC regular data register(ADC_DR)24210.13. 15 ADC Common status register(ADC_CSr)24410.13. 16 ADC common control register (ADC_CCR)10. 13.17 ADC common regular data register for dual and triple modes(ADC- CDR)24710.13. 18 ADC register map247Digital-to-analog converter(DAC)∴.…■■■■■■■■■■■■■■■■■25011.1 DAC introduction25011.2 DAC main features25011.3 DAC functional description25211.3.1 DAC channel enable....25211.3.2 DAC output buffer enable25211.3.3 DAC data format25211.3.4 DAc conversion25311.3.5 DAC output voltage25411.3.6 DAC trigger selection25411.3.7 DMA request..25411.3.8 Noise generation.,.25511.3.9 Triangle-wave generation11.4 Dual dac channel conversion2574.1 Independent trigger without wave generatie25711. 4.2 Independent trigger with single LFSR generation25811.4.3 Independent trigger with different LFSR generation25811.4.4 Independent trigger with single triangle generation.25811.4.5 Independent trigger with different triangle generation251. 4.6 Simultaneous software start25911.4.7 Simultaneous trigger without wave generation.25911.4.8 Simultaneous trigger with single LFSR generation26011.4.9 Simultaneous trigger with different LFSR genera26011.4.10 Simultaneous trigger with single triangle generation,2604.11 Simultaneous trigger with different triangle generation2611.5 DAC registers26111.5.1 DAC control register(DAC_Cr)11.5.2 DAC software trigger register(DAC_ SWTRIGR).264DOC ID 018909 Rev 1/131ContentsRM009011.5.3 DAC channel1 12-bit right-aligned data holding registerDAC_DHR12R1).26411.5.4 DAC channel1 12-bit left aligned data holding register(DAC_DHR12L1).26511.5.5 DAC channell 8-bit right aligned data holding registerDAC_ DHR8R1)....26511.5.6 DAC channel2 12-bit right aligned data holding register(DAC_DHR12R2.26511.5.7 DAC channel2 12-bit left aligned data holding register(DAC_DHR12L2...26611.5.8 DAC channel2 8-bit right-aligned data holding register(DAC_DHR8 R2)26611.5. 9 Dual DAC 12-bit right-aligned data holding register(DAC_DHR12RD)26611.5.10 DUAL DAC 12-bit left aligned data holding register(DAC_DHR12LD).26711.5.11 DUAL DAC 8-bit right aligned data holding registerDAC_ DHR8RD).,,26711.5. 12 DAC channell data output register(DAC_DOR1)26811.5. 13 DAC channel2 data output register(DAC_DOR226811.5. 14 DAC status register(DAC_SR).26811.5.15 DAC registe26912Digital camera interface(DCMI)27012.1 DCMI introduction27012.2 DCMI main features27012.3 DCMI pins27012.4 DCMI clocks.27012.5 DCMI functional overview27112.5.1 DMA interface27212.5.2 DCMI physical interface.··27212.5.3 Synchronization,,.27412.5.4 Capture modes.27612.5.5 Crop feature..27712.5.6 JPEG format27812.5.7F|FO27812.6 Data format description27912.6.1 Data formats,.,.,,27912.6.2 Monochrome format27910/1316DOC ID 018909 Rev 1