ISSCC2017-04

ISSCC2017-04 Session 4 Overview: ImagersISSCC 2017/ SESSION 4/IMAGERS /4.1A 640x480 Dynamic vision Sensor with a 9um Pixel Compared with previous works [ 1-6] that process events pixel-by-pixel withand 300Meps Address-Event RepresentationERhandshaking, which results in slow data throughput, G -AER can increase the aEdata rate considerably. To increase the data rate up to 300 Meps, severalneighboring pixels in the column are grouped and dealt with like a single pixelBongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, while oN and OFF events of the pixels in the same group are processed in parallelFigure 4.1.3 illustrates the structures and the conceptual timing diagram of gJooyean Woo1, yohan Roh hyunku Lee, Yibing Wang?,AER. The 480b ON and OFF events from RSC are divided into 60 groups byllia Ovsiannikov2, Hyunsurk Ryuhandling every neighboring 8 pixels as a unit and merged by 60 independent 16-input ORs whose output(GrpFlagIn) indicates whether any events exist in each'Samsung Advanced Institute of Technology, Suwon, Koreagroup or not. The following FastFinder takes 60b Grp FlagIn and searches theSamsung Electronics, Pasadena, CAlocation of 1-valued digit from LSB to MSB without redundant CLK cycle. Then,with the output of FastFinder(GrpFlagOut)at every CLK cycle, the group addressWe report a VGA dynamic vision sensor( DVS)with a 9um pixel, developed encoder and group event selector output its corresponding group address andthrough a digital as well as an analog implementation DVs systems in the oN/OFF event data. The operating example of FastFinder including the output ofliterature try to increase spatial resolution up to QVGA[1-2]and data rates up to G-AER is given in Figure 4.1.3. G-AER is fully synthesized at a timing constraint50 million events per second(Meps )(self-acknowledged)[3], but they are still of 5OMHz, thus it is possible to increase the data processing capacity overinadequate for high-performance applications such as gesture recognition, 300Meps by synthesizing at a timing constraint of more than 50MHz with nodrones,automotive, etc. Moreover, the smallest reported pixel of 18 5um is too modification in the designlarge for economical mass production 3. T his paper reports a 640x480 VGAresolution DVS system with a 9um pixel pitch supporting a data rate of 300Meps The 640x480 DVS is implemented in a 90nm 1 P5M BSI CIS process and occupiesr sufficient event transfer in spite of higher resolution Maintaining acceptable 80x5.8mm2. The measured performance results are summarized in Fig. 4.1.6pixel performance, the pixel circuitry is carefully designed and optimized using a The chip consumes a total of 27 mW at a data rate of 100keps and 50mW atBSI CIS process. To acquire data (i. e, pixel events)at high speed even with high 300Meps. The power consumption per pixel is 88nw and 160nw at 100keps andresolution(e.g, VGA), a fully synthesized word-serial group address-event 300Meps, respectively. Several measurement results are shown in Fig 4.1.4.Therepresentation(G-AER)is implemented, which handles massive events in parallel rotating image with about 400rpm is captured by conventional CIS and DVSby binding neighboring 8 pixels into a group In addition, a 10b programmable prototype cameras at the collecting time (at)of from 16.7 to 0.25ms. The lettersbias generator dedicated to a dvs system provides easy controllability of pixel on the dvs image are clear while they are blurred on the cis image. Two imagesbiases and event thresholewere taken at the different contrast sensitivities of 9 and 25%. the second linefrom the bottom). The environment for testing dynamic range is shown at the leftFigure. 4.1.1 illustrates a DvS pixel circuit, composed of a gain- boosted log image on the bottom. The dynamic range is verified by checking that DVS canamplifier(LOGA), a source follower, a capacitive- feedback amplifier (CFA) see bright and dark area at the same time. In result, right image shows DVSfollowed by comparators, and 4-phase handshaking logic [3]. Previously, such achieves wide dynamic range of >80dB. Figure 4.1.5 shows the measuredcircuit complexity had impeded the development of pixels smaller than 100um?, transient data rate of the image recorded by DVS. The fixed image was taken withwhile keeping the contrast sensitivity less than 10% due to a design tradeoff. This turning the light on and off. The chip photograph and pixel layout are shownconstraint is resolved by distributing pixel gain between LOGA and CFA and Fig. 4.1.7implementing the DVS in a BSI CIS process. The stacked transistor, MLogtenhances the gain of the LoGa by (1+n ), where n is the subthreshold slope factor, Referencesand thus leads the improvement in the contrast sensitivity in spite of decreasing [1]C. Li, et al.,"An RGBW Color VGa Rolling and Global Shutter Dynamic andthe capacitive ratio, C, /C,, of cfa due to reduction in pixel pitch. Also, MNz is Active-Pixel vision Sensor, "IEEE / SCAS, pp. 718-721, 2015cascoded to avoid bW degradation introduced by the additional pole at the drain [2]C. Posch, et al. , "a QVGa 143dB Dynamic Range Asynchronous Addressnode of MN2. Furthermore, a conventional dVs pixel structure is vulnerable to Event PWM Dynamic Image Sensor with Lossless Pixel-Level videoperiodic false events caused by the substrate leakage current from the power Compression, /SSCC, pp. 400-401, Feb 2010supply to the floating node, VIrl, via a reset transistor, MRESET. Periodic false events, [3] C. Brandi, et al., " a 240 x 180 130 db 3 us Latency Global Shutterunnecessarily consuming AER bandwidth, are addressed by fetching the leakage Spatiotemporal Vision Sensor, "IEEE JSSC, voL 49, no 10, pp. 2333-2341, 2014path by tying the body of mReser to the output of CFA. The tied body could limit [4] T. Serrano-Gotarredona, et al. " A 128 x 128 1.5% Contrast Sensitivity 0.9%the output voltage swing when the drain-body junction of RESet is forward-biased, FPn 3 us Latency 4 mW Asynchronous Frame Free Dynamic Vision Sensor Usingthe event threshold voltages are set below 0. 25V not to be affected by the limited Transimpedance Preamplifiers, IEEE JSSC, volL. 48, no 3, pp. 827-838, 2013swing. All current biases are supplied by a 10b programmable bias generator, [5]J. A Lenero-Bardallo, et al. "A 3. 6us Latency Asynchronous Frame-free Eventalso shown in Fig 4.1.1. Pre-defined current sources are used for 3b coarse driven Dynamic-vision-sensor, "IEEE JSSC, vol 46, no 6, pp. 1443-1455, 2011tuning, and 7b fine tuning is provided to achieve a wide dynamic range by the [6]P Lichtsteiner, et al. ,"A 128 128 120db 30mW Asynchronous Vision Sensorvoltage drop across the programmable resistor bank in the feedback loop of amp that Responds to Relative Intensity Change, "SSCC, pp. 508-509, Feb 2006Since all bias transistors operate in the subthreshold region, IBiAs exponentiallyincreases along with an increase in 7b fine tuning code while vbias linearlyincreases. Thus, a wide dynamic range is easily achieved without redundant bitsigure 4.1.2 shows the architecture of the dvs system with a 640x480 pixel array,Fⅰa column AER, a row sampling circuit (rsc), a 10b programmable bias generator,and a fully synthesized G-AER. When events occur in pixels, the column AERsends a column request (ReqCol)and its corresponding column address(AddrXto G-AER G-AER sends an acknowledgement(Ackcol) based on a handshakinglogic and a whole 960-pixel data(regy oN, rear oFf)in the correspondingcolumn are sent to RSC. Then, RegY_on and regy_ oFF are sampled with Ackcoland the sampled results(ON, OFF)are sent to G-AER With these ON and OFFdata, G-AER generates a 10b column address(AddrX_buf), 6b group address(AddrYGrp, each 8b ON and OFF events (ONGrp OFFGrp), and 32b timeinformation(Time Stamp). The architectural timing diagram is also presented inFig.4.1.2662017 EEE International Solid-State Circuits Conference978-1-5090-37582/17/$31.00@2017|EEISSCC 2017/February 6, 2017/1: 30 PMco|umn厶ERBlas generatorPixelColumn Aerw“"EXT CLK420MHZY1-b switch6.b RTuNE日鬻Reset AckX6AckvMmCOLyyyVREFby MocrAccorOff thresholdk几…几几几几几几∏. 7be-hing exe3.b coarse tuningvAs=Me· inGERSonOFF3rp 0]=14405Figure 4.1.1: Pixel and bias generatorFigure 4.1.2: DVS architecture and timing diagram.GrouP EwtGrp[:CIOriginaGp[0SrPFlgoutDEDVSgroup addres IAddrY Grp 5: D)Log2|1c0000=)VSGrpFla goutDVSDVS△=0.5m△=025msSDVSDYSFast Finderout pu Qf G-AER, wan543210CX2X-…Xux)Lux)Gray No eventWhite ON0365T40Fe…恩arkBlack OFFAddrX_ BUFI:o]…<_uX) (100KLun) Yellow ON/OFFFigure 4.1.3: Diagrams of Group aer and FastFinder.Figure 4.1.4: Speed, sensitivity and WDR of DVsLight ONLight OFF1.000.0Data Ratehis worksc14ss13{|ssc11同|c06间nogy■90m5MBs■018mP6N035m2P4M035m?P4M■035um2P4MResolE tion640X480240X180128X128128x128Chip Area(mm2)8X549X4955X566X6330X3135X35Power supply28V analog18V3.3V(piⅸxes)33V3.341.2v digital290MepsPower 1C0Keps I14mw(high activimw(low a stivyPower/Picel 1coKepsI 0.0880.32 (high activly) 0.24B06146uW/)300Meps 0.16012 (low activityPower/Event 1C0KepsRate(nW) 300Meps I0171505ensitivity(‰)1.0253.0Time(sec)Max. Event Fate0050(self ack)12(CPLDOriginalChip InterfaceMIP. USBConnectable I/F 12CHandshakeHandshake Handshake123easured average pawer of 30 samples. PLL power(Smw) is inA BCA BIC6. Total power normalized to resolutionC. Total power normalized to max event rate-k d. The total power of this work includes IO power and digital interface. Others do notRed pixel -representing ONThe sampled frames by time iowGreen pixe/-representing OFF eventBlack pixel -representing no ewentFigure 4.1.5: Transient data rate recorded by dvsFigure 4.1.6: Comparison with state of the artDIGEST OF TECHNICAL PAPERS67ISSCC 2017 PAPER CONTINUATIONS8mmLaw www-wwwwmiw -www wuuColum AER640×480 Pixel Array(9um x 9um)Pixel LayoutaPdiode10-bit Programmable Bias Generator2” meam wNw=m置置Figure 4.1.7: Micrograph of Dvs chip in BSI process2017 EEE International Solid-State Circuits Conference978-1-5090-37582/17/$3100@2017EEEISSCC 2017/ SESSION 4/IMAGERS /4.24.2 A Fully Integrated cMos fluorescence Biochip for Figure 4.2.3 shows the detailed pixel circuitry and the timing diagram of the chargeMultiplex Polymerase Chain-Reaction(PCR)subtraction (4 operation) based on Dour. The oversampling clock,ProcessesCLK-A =100kHz, triggers the comparator and the generated dour chooses betweentwo 100KHz clockS, CLK, and CLK 2, with different duty cycles to divert IREF= 1HAinto the ctia input. the pulse durations are programmable between 10 to 100nsArjang Hassibi, Rituraj Singh, Arun Manickam, Ruma Sinha,in every 10us, corresponding to 1-to-10nA continuous current subtraction, whichBob Kuimelis, Sara Bolouki, Pejman Naraghi-Arani, Kirsten Johnson, accommodates tunable charge subtraction for both low and high-gain modesMark McDermott, Nicholas Wood, Piyush Savalia, Nader GaminiThe optical performance of the pixels without the emission filter is shown in figIn Silixa, Sunnyvale, CA4.2. 4. The maximum external QE is -42% at 650nm and the measured detectiondynamic range >10. The SNR in high-gain mode is -1 db below shot-noise limitIntegration and miniaturization of bio-molecular detection systems into electronic for lp4> 15tA and limited by quantization noise below that level. As evident, thebiosensors and lab-on-chip platforms is of great importance. One widely pixel dark current, ID can become significant when measuring at assayrecognized application area for such devices is nucleic acid(DNA and RNA temperatures >70"C. To mitigate this, we use correlated double sampling at eachdetection, specifically, nucleic acid amplification testing(NAAT), which relies on temperature, subtracting two measurements, one with the LEd on and one withenzymatic processes such as polymerase chain reaction(PCR)to increase the the Led offcopy number of target sequences and detecting them spectroscopically [1, 2The SEM cross-section of the pixel with emission filter is shown in Fig. 4.2.5. ThisHere, we present a fully integrated CMOS DNA biosensor array(biochip)for filter is a long-pass multi-dielectric (TiO2 and Sio,) interference filter designedclinical NAAT capable of performing multiplex(parallel)PCR in one 40UL reaction and fabricated at wafer level with a cut-off wavelength of 585nm. Like allchamber using on-chip thermo-cycling (+4 C sec-heat/cool rate), real-time interference filters, the transmittance is a function of angle of incidence(AOl)andamplicon-probe hybridization detection(up to target 1000 unique sequences), shifts to lower wavelength at higher Aols. This characteristic significantlyand solid-phase(surface)melt-curve analysis from 40 to 90%C with 0.3c diminishes a for Fx in high-scattering aqueous media of biosensors and lab-onresolution. The detection modality is continuous-wave fluorescence with an chip. To address this challenge, we specifically optimized the layer thicknesseseffective pass-band to stop-band optical density(OD)of -3.6 using an inverse to have minimal shift vs. AOl and took advantage of a dual-fluorophore structurefluorophore assay [3 that requires no labeling, or sandwich probes [4]in the to increase the fluorescence Stokes shift. In this structure, two fluorophores,reaction mix. Unlike electro-analytical biochips [5], the transducer surface as well namely fluorescein( FAM)and tetramethylrhodamine(TAM), are conjugatedas surface chemistries of this system, are chemically and thermally stable and do close proximity to each other on the end of DNA probe the excitation of FAM atnot degrade during PCR thermo-cycling490nm can therefore result in the fluorescence resonance energy transfer to tamdue to the fAM-TAM emission-absorption spectral overlap and produce emission4.2.1, the biochip module and its 32x32 biosensing pixels is illustrated. at 580nm, enhancing the Stokes shift to >90nm. As shown in the Fig. 4.2.5, theThe 7x9mm2 die is packaged on a thermally conductive PCB substrate. a flowuse of FAM-TAM in addition to optimizing the filter, ensures minimal fx leakagethrough and optically transparent fluidic cap is mounted on it such that its sensing at AOl 50 and effective OD remains around 3.6surface is exposed to the reaction( PCr) chamber and accessible only throughthe fluidic inlet and outlet. Each 100x100um? biosensor (pixel)includes a CMoS- In Fig. 4.2.6, an example usage of this biochip, enabling a respiratory infectionintegrated photo-sensor and a resistive heater. Each pixel is further augmented panel NAAT, is shown. A 7-plex Pcr in the reaction chamber simultaneouslyby a multi- dielectric interference filter( fabricated post-CMOS) and fluorogenic amplifies unique sequences of the 7 viruses listed FluA, Flub, etc. )using on-chipDNa capture probes covalently attached to its SiO 2 surface using a silanization thermal cycling. All 14 PCR primers include a quencher molecule. On successfulprocess. An external LED source is utilized to excite the fluorophore conjugated PCR amplification, if the targets are present in the chamber, amplicons withto the capture probesquenchers are generated Such amplicons, are then captured by the matchingDNA probes, and modulate(reduce) the FAM-TAM signal at the correspondingThe biosensing pixel block diagram and the chip architecture are shown in Fig. pixel (i.e, inverse fluorescence method). The measured results demonstrate that,4.2.2. The LED excitation flux, Fx, passes through the transparent fluidic cap andusing this method and the biochip we can identify the presence of theseexcites the luorogenic probes to emit photon flux FE, at longer wavelengths viruses in the sample by measuring the fluorescence signal at the pixels and(typically >20nm). Both Fy and F: hit the emission filter, which is specifically further validate the result by analyzing the DNa-amplicon melt-curvedesigned to preferentially black Fx and allow Fe to pass. It is important to notethat while a, the attenuation level of Fx, is high( e.g., a> 10 ) in practical Referencesfluorescence assays, FE< FX/a, which requires the high-dynamic range photo- [1]C. Zhang and D. Xing, "Miniaturized PCR Chips for Nucleic Acid Amplificationsensor to detect small signals in presence of a large backgroundand Analysis: Latest Advances and Future Trends", Nucleic Acids Res, voL. 35n0.13,2007.o address this impediment we take advantage of a unipolar A2 photo-sensor [2]A Hassibi, "CMOS Biochips for Point-of-care Molecular Diagnostics, Hotcircuit in each pixel to maximize the effective well-capacity without compromising Chips, 2014the noise performance. As shown in Fig. 4.2.2, the photocurrent, Iy, generated [3]A. Hassibi, et al. "Real-time DNA Microarray Analysis", Nucleic Acids Resoy the in-pixel nwell-psub photodiode, is first integrated by a CTIA(2 operation ). voL 37, no 20 2009Subsequently, the CTIA output is compared to a fixed reference voltage by a [4]H. Wang, et al, "A Frequency-shift CMOS Magnetic Biosensor Array withclocked comparator(quantizer) and its output, DouT, triggers the subtraction of Single-bead Sensitivity and No External Magnet", ISSCC, pp. 438-439, Feb. 2009the appropriate charge(AO, or AO,)from the CTIA (A operation)[5P. M. Levine, et al., Active CMOS Sensor Array for ElectrochemicalBiomolecular detection" /EEE JSSC. vol, 43. no 8 2008All 1024 individual pixels, including 13 temperature-sensor pixels that havecovered photodiodes can individually be addressed. by using row and columndecoders, the digital (DouT(i,j)) and analog(aou(i, j))outputs are brought off-chipusing serialized LvDs buffer and multiplexed analog column amplifiers,respectively. The chip includes a passive 10W multi-finger resistive heaterintegrated using the top metal layer with traces in every pixel682017 EEE International Solid-State Circuits Conference978-1-5090-37582/17/$31.00@2017|EEISSCC 2017/February 6, 2017/2: 00 PMHEATER(+HEATER(y+4+++XCITATION FUX (FlDNAsFLU OREMISSION FILTERCAPTUREANRIOG COLUM N AMMFLI FIERSBIOSENSING PIXELFLUX(F)+BIOCHIPFILTERHEATERPHOTODIODECOLUMN DECO DER+ MULTIPLEEACTIONoPHOTODIODECONTROL Dour(i j)pA会确RFigure 4.2.1: CMOS fluorescence biochip with DNA-functionalized optical Figure 4.2.2: Chip architecture, functional block diagram, and layout of thepixelsbiosensing pixel.CHARGE SUBTRACTOR (DAC)-044CL别2|2COMPARATORPHOTODIODEROW800900SAMPLE/HoLD一Wavelength (nm)CTIAo萨AMPFEEDBACKCLK1R measured(High gainNR mea sured (Low gainO,NR accelFigure 4.2.3: Biosensing pixel circuitry and timing diagram for charge Figure 4.2.4: Measured optical performance of the pixel (without emissionsubtraction(A operation)filter)DNA ProbesPOR CYCLESMELTEmission Filter"SET:\MEASUREDPhotodiodeCircuitryS日150kX750WD8/mm1000 50 0 iCse700000000A MPLIONSPmE序cENH团RQUEVCHEAo=20A01=50°RSVFAM-TAM AbsFAM-TAMET4-)CantrelWavelength nm)Figure 4.2.6: On-chip 7-plex polymerase chain reaction(PCR)process for anFigure 4.2.5: Cross-section SEM of the pixel, measured external QE (with filter), upper respiratory viral detection panel and the measured melt-curve resultsand FAM-tAM measured spectrafrom 8 different targetsDIGEST OF TECHNICAL PAPERS69ISSCC 2017 PAPER CONTINUATIONSI HEATER(+):lmi#!!:s!!!s! SHASARRAYLUIULROW DECODERLLLLLL1mmHEATER( HhHH,w付Figure 4.2.7: Die micrograph2017 EEE International Solid-State Circuits Conference978-1-5090-37582/17/$3100@2017EEEISSCC 2017/ SESSION 4/IMAGERS /4.34.3A Programmable sub-Nanosecond Time-Gated 4-Tap Figure 4.3.3 shows the chip diagram of the TR cis, and measurement conceptualLock-In Pixel CMOS Image Sensor for Real-Timediagram using 4-tap and measured output signals from each PSd with 472nmFluorescence Lifetime Imaging Microscopypulsed laser diode scanning(Laser pulse width: 120ps). The sensor consists ofa 4-tap TR lock-in pixel array(128(H)x128(V)), built-in pixel-level LEFM PG forgates (TG1 to TG4, and TD), inverter tree with clock driver, low-noise and wideMin-Woang Seo, Yuya Shirakawa, Yuriko Masuda, Yoshimasa Kawata, dynamic range column-parallel ADCs, a digital logic block for on-chip dataKeiichiro Kagawa, Keita Yasutomi, Shoji Kawahitoprocessing, and verticalhorizontal scanner for pixel addressing as can be seenfrom the conceptual diagram(upper right) for 4-tap lock-in pixel implementation,Shizuoka University Hamamatsu Japanfour points on the fluorescent decay profile are simultaneously captured bygenerated sub-nanosecond TWs. It makes possible to detect multiple lifetimeFluorescence-based time-resolved(TR )analysis techniques are fundamental and components of sample without TW scanning(or with a little TW scanning). At theeffective methods in life science and medicine. Among others, fluorescence same time, a FLT measurement time is also dramatically reduced in comparisonlifetime imaging microscopy(FLIM)is one of the representative measurement with a conventional scanning method. A high SNR real-time FLT measurementtechniques for biomedical applications Recently advanced all-solid-state imaging system can be realized by using the FLIM sensor with sub-nanosecond TWsdevices for FLIM, e.g., a CCD with optional electron-multiplication (EM)readout,a single-photon avalanche diode (SPAD), and a tr MoS image sensor(cIS), By using the prototype FLlM sensor, the FLts of different types of fluorescenthave been reported [1-3]. These devices can be implemented compactly in acrylic panel (blue, green, and orange)are measured, as shown in Fig4.3.4.Thehacomparison with the typical FLIM systems such as a time-correlated single- left-hand side result of this figure is measured by a conventional time-gatingphoton counting(TCSPC)system [4]. However, imaging devices based on the method with a time delay. The measured FLT values are very close to the referenceCCD or SPAD still have some issues, including the need for specialized fabrication FLT values, which are measured by a TCSPC system, without any compensations,processes, use of higher voltages, and greater circuit complexity the recent tr e.g. the flt of blue acrylic panel=1.ins(reference value: 0. gns), green=3.OnsCIS with two taps in a pixel [3] shows us a way to realize real-lime lifetime (3.Ons), and orange=.4ns (6.7ns). The right-hand side result of Fig. 4.3.4imaging but the two-tap ciS has a limitation that a sample's lifetime cannot be demonstrates the effectiveness of 4-tap pixel. As can be seen from this resultmeasured in real time if the sample has multi-exponential decay components. (right), only a few frames (2 or 3 frames )are good enough to estimate the FLtdecaying curve of the sampleThis paper presents a sub-nanosecond time-gated four-tap lock-in pixel CIS usingin-pixel pulse generator(PG)for fluorescence lifetime(FLT) imaging system. To Figure 4. 3.5 shows a color FLT image of HeLa-cell with DAP (nucleus), bound torealize a real-time FLT measurement system, good low-noise performance and F-actin, and ATT0488 modified with phalloidin, which are excited by 374nm andthe capability for fast data acquisition are essential. Thus, a lateral electric field 472nm laser diodes, respectively. The left is an intensity image of the fluorescentcharge modulator(LEFM)implemented with in-pixel PG block, 2-stage charge- sample captured by the developed TR CIS with 472nm excitation. Observed twotransfer technique for true correlated double sampling(CDS )operation and FLT components ot DAPI(Emi. Max =461nm)and All0488-phalloidinmulti-tap design are used for the developed lock-in pixel. Additionally, a narrow (Emi. =523nm) are mapped with different colors as shown in this figure (right),time-Window(TW)generated in pixel-level PG helps to attain the high signal-to- and the measured FLTs of DAPI and ATTo488-phalloidin are approximately 3 tonoise ratio (SNR)FLT measurement results4ns and 5 to 6ns, respectively. A very clear FLT image of a single cell is attainedby the flim imager, even though two flt values of daPl and atto488-phalloidinFigure 4.3. 1 shows the sub-nanosecond time-gated lock-in pixel structure with are quite close. The sensor performance and characteristics are summarized infour output ports and its equivalent circuit schematic diagram the pixel is Fig. 4.3.6. This sensor has the extremely low temporal random noise level ofcomposed of a pinned photodiode(PPD), four in-pixel pinned storage diodes 0.85e-rms at 45fps, relatively large full-well capacity(FWC )of each PSD ofPSDs), four sets of LEFM gates(TGs)with TD gate for draining the undesirable 5500e-, and high pixel conversion gain of 133uv/e, as well as very fast intrinsiccharges, and PG block, which is shared by adjacent two pixels, for fast charge response of 170ps at 472nmmodulation As can be seen in the equivalent pixel circuit diagram, each of foursource follower' s outputs from each pixel is connected to each of four low-noise Acknowledgement.column readout circuits based on correlated multiple sampling technique. The This work was supported in part by the Grant-in-Aid for Scientific Research(S)gates, TGs, make it possible to modulate the signal charges at the aperture area. under Grant 25220905 through the Ministry of Education, Culture, Sports,By the LEFM control clocks(CK_TG1 to CK_TG4 ), the signal charge is transferred Science, and Technology(MEXT), in part by the MEXT/JST COI-STREAMto the targeted PSD from PPD. After finishing a gating operation to capture the program, and in part by the vlsi Design and Education Center (VDEC), thesignal, the td gate is always opened by CK_td to clean the ppD and University of Tokyo in collaboration with Cadence Design Systems, Inc. andsimultaneously to reduce the parasitic light sensitivity(PLS). Each PSD has a Mentor Graphics, Inc. Also, authors appreciate Dongbu HiTek for CIS chipquite large full-Well capacity(FWc)of 5500efabricationFigure 4.3.2 shows the in-pixel PG blocks to make a very narrow TW<1ns. the Referencesinternal PG block can be divided neatly into two parts. the first part is a delayed [1]J. Osiers, et al., " MEM-FLIM, a CCD Imager for Fluorescence Lifetime Imagingpulse generator (DPG)with tunable delay unit (0. 8 to 2.6ns )using a current- Microscopy, "Int Image Sensor Workshop, pp 53-56, June 2013starved inverter(CSl)chain, and the other is a sub-nanosecond LEFM pulse [2]M. Perenzon, et al., "A 160x120 pixel Analog-counting Single-photon Imagergenerator(SLPG)for making sub-nanosecond TW. An input pulse from the with Time-gating and Self-referenced Column-parallel A/D Conversion forexternal timing generator is entered into the DPG via many repeater clock buffers Fluorescence Lifetime Imaging, "IEEE JSSC, vol. 51, no. 1, pp. 155-167, Janon chip to reduce the parasitic capacitance component effect the input pulse is 2016delayed by six delay units, which consists of the CSls, into the DEl to DE6. Each [3]M. W Seo, et al.,"A 10ps Time-resolution CMOS Image Sensor with Two-tapminimum delayed time is approximately 0. ns, and it is equal to the minimum True-CDS Lock-in Pixels for Fluorescence Lifetime imagiIEEE JSSC. voL. 51pulse width of the TW. The delayed pulses(DE1 to DE6)are connected to each no. 1, pp. 141-154, Jan 2016PG unit in the SLPG. The PG unit is composed of a few logic gates, a multiplexer [4]W. Becker, Advanced Time-Correlated Single Photon Counting Techniquesfor choosing an internal/external operation mode, and an lEfm driver with Vh New york, Ny, USA: Springer, vol. 81, 2005(high-level voltage)and VL(low-level voltage). By using these in-pixel PGs, a verynarrow TW(

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