fpga分频程序

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdiv50mISPORT(clk:INSTD_LOGIC;co:OUTSTD_LOGIC);ENDdiv50m;ARCHITECTUREfunOFdiv50mISSIGNALq:INTEGERrange0to50000000-1;BEGINPROCESS(clk)BEGINIF(clk'EVENTANDclk='1')THENIFq