简单verilog testbench

简单verilogtestbench`timescale1ns/1nsmoduletb_jet_ctrl_top();parameterU_DLY=1;integeri;regrst_n;regclk;reg[7:0]cpu_dat;reg[11:8]cpu_addr;regcpu_cs;regcpu_wr_n;regprt_trig_n;initialbeginrst_n=1'd0;