DMSoC Clock Reference Generator (CRGEN)

Preface ............................................................................................................................... 6 1 Introduction................................................................................................................ 7 1.1 Purpose of the Peripheral...................................... ................................................. 7 1.2 Features ........................................................................................................... 7 1.3 Functional Block Diagram....................................................................................... 7 1.4 Terminology Used in This Document.......................................................................... 8 2 Architecture ............................................................................................................... 8 2.1 Clock Control ..................................................................................................... 8 2.2 Signal Descriptions .............................................................................................. 8 2.3 Pin Multiplexing................................................................................................... 8 2.4 Functional Description........................................................................................... 8 2.5 Processing Method of Clock Recovery ...................................................................... 10 2.6 Software Configuration......................................................................................... 10 2.7 Hardware Reset Considerations.............................................................................. 11 2.8 Interrupt Events and Requests ............................................................................... 11 2.9 Emulation Suspend Mode Support........................................................................... 11 3 Registers.................................................................................................................. 11 3.1 CRGEN Peripheral Identification Register (PID) ........................................................... 12 3.2 CRGEN Control Register (CONTROL) ...................................................................... 13 3.3 STC Counter Current High Value Register (STC_HI) ..................................................... 14 3.4 STC Counter Current Low Value Register (STC_LO) ..................................................... 14 3.5 STC Counter High Value Register (STC_VAL_HI)......................................................... 15 3.6 STC Counter Low Value Register (STC_VAL_LO) ........................................................ 15 3.7 PCR Counter High Value Register (PCR_HI)............................................................... 16 3.8 PCR Counter Low Value Register (PCR_LO) .............................................................. 16 3.9 PCR Packet Status Register (PCR_PKT_STAT)........................................................... 17 3.10 Loop Filter Register (LOOP_FILTER)........................................................................ 17 3.11 STC Counter Offset High Value Register (STC_OFFSET_HI) ........................................... 18 3.12 STC Counter Offset Low Value Register (STC_OFFSET_LO)........................................... 18 3.13 Interrupt Enable Register (INTEN) ........................................................................... 19 3.14 Interrupt Enable Set Register (INTEN_SET)................................................................ 20 3.15 Interrupt Enable Clear Register (INTEN_CLR) ............................................................. 20 3.16 Interrupt Status Register (INTSTAT)......................................................................... 21 3.17 Interrupt Status Clear Register (INTSTAT_CLR)........................................................... 21 3.18 Emulation Control Register (EMU_CTRL)................................................................... ................................................. 7 1.2 Features ........................................................................................................... 7 1.3 Functional Block Diagram....................................................................................... 7 1.4 Terminology Used in This Document.......................................................................... 8 2 Architecture ............................................................................................................... 8 2.1 Clock Control ..................................................................................................... 8 2.2 Signal Descriptions .............................................................................................. 8 2.3 Pin Multiplexing................................................................................................... 8 2.4 Functional Description........................................................................................... 8 2.5 Processing Method of Clock Recovery ...................................................................... 10 2.6 Software Configuration......................................................................................... 10 2.7 Hardware Reset Considerations.............................................................................. 11 2.8 Interrupt Events and Requests ............................................................................... 11 2.9 Emulation Suspend Mode Support........................................................................... 11 3 Registers.................................................................................................................. 11 3.1 CRGEN Peripheral Identification Register (PID) ........................................................... 12 3.2 CRGEN Control Register (CONTROL) ...................................................................... 13 3.3 STC Counter Current High Value Register (STC_HI) ..................................................... 14 3.4 STC Counter Current Low Value Register (STC_LO) ..................................................... 14 3.5 STC Counter High Value Register (STC_VAL_HI)......................................................... 15 3.6 STC Counter Low Value Register (STC_VAL_LO) ........................................................ 15 3.7 PCR Counter High Value Register (PCR_HI)............................................................... 16 3.8 PCR Counter Low Value Register (PCR_LO) .............................................................. 16 3.9 PCR Packet Status Register (PCR_PKT_STAT)........................................................... 17 3.10 Loop Filter Register (LOOP_FILTER)........................................................................ 17 3.11 STC Counter Offset High Value Register (STC_OFFSET_HI) ........................................... 18 3.12 STC Counter Offset Low Value Register (STC_OFFSET_LO)........................................... 18 3.13 Interrupt Enable Register (INTEN) ........................................................................... 19 3.14 Interrupt Enable Set Register (INTEN_SET)................................................................ 20 3.15 Interrupt Enable Clear Register (INTEN_CLR) ............................................................. 20 3.16 Interrupt Status Register (INTSTAT)......................................................................... 21 3.17 Interrupt Status Clear Register (INTSTAT_CLR)........................................................... 21 3.18 Emulation Control Register (EMU_CTRL)...................................................................