Jitter Transfer Characteristics of Delay-Locked

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we showthat in a widely used DLL configuration,jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filt ering and phase filtering are discussed.Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.