ARM体系架构参考手册

ARM架构参考手册，英文原版： ARM Architecture Reference Manual Part A Chapter A1 Chapter A2 Preface About this manual ................................................................................ xii Architecture versions and variants ...................................................... xiii Using this manual ............................... ............................................... xviii Conventions ........................................................................................ xxi Further reading .................................................................................. xxiii Feedback .......................................................................................... xxiv CPU Architecture Introduction to the ARM Architecture A1.1 About the ARM architecture ............................................................. A1-2 A1.2 ARM instruction set .......................................................................... A1-6 A1.3 Thumb instruction set ..................................................................... A1-11 Programmers’ Model A2.1 Data types ........................................................................................ A2-2 A2.2 Processor modes ............................................................................. A2-3 A2.3 Registers .......................................................................................... A2-4 A2.4 General-purpose registers ............................................................... A2-6 A2.5 Program status registers ................................................................ A2-11 ARM DDI 0100I Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. v Contents Chapter A3 A2.6 Exceptions ..................................................................................... A2-16 A2.7 Endian support ............................................................................... A2-30 A2.8 Unaligned access support .............................................................. A2-38 A2.9 Synchronization primitives ............................................................. A2-44 A2.10 The Jazelle Extension .................................................................... A2-53 A2.11 Saturated integer arithmetic ........................................................... A2-69 The ARM Instruction Set A3.1 Instruction set encoding ................................................................... A3-2 A3.2 The condition field ............................................................................ A3-3 A3.3 Branch instructions .......................................................................... A3-5 A3.4 Data-processing instructions ............................................................ A3-7 A3.5 Multiply instructions ........................................................................ A3-10 A3.6 Parallel addition and subtraction instructions ................................. A3-14 A3.7 Extend instructions ......................................................................... A3-16 A3.8 Miscellaneous arithmetic instructions ............................................ A3-17 A3.9 Other miscellaneous instructions ................................................... A3-18 A3.10 Status register access instructions ................................................ A3-19 A3.11 Load and store instructions ............................................................ A3-21 A3.12 Load and Store Multiple instructions .............................................. A3-26 A3.13 Semaphore instructions ................................................................. A3-28 A3.14 Exception-generating instructions .................................................. A3-29 A3.15 Coprocessor instructions ............................................................... A3-30 A3.16 Extending the instruction set .......................................................... A3-32 ARM Instructions A4.1 Alphabetical list of ARM instructions ................................................ A4-2 A4.2 ARM instructions and architecture versions ................................. A4-286 ARM Addressing Modes A5.1 Addressing Mode 1 - Data-processing operands ............................. A5-2 A5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte ...... A5-18 A5.3 Addressing Mode 3 - Miscellaneous Loads and Stores ................. A5-33 A5.4 Addressing Mode 4 - Load and Store Multiple ............................... A5-41 A5.5 Addressing Mode 5 - Load and Store Coprocessor ....................... A5-49 The Thumb Instruction Set A6.1 About the Thumb instruction set ...................................................... A6-2 A6.2 Instruction set encoding ................................................................... A6-4 A6.3 Branch instructions .......................................................................... A6-6 A6.4 Data-processing instructions ............................................................ A6-8 A6.5 Load and Store Register instructions ............................................. A6-15 A6.6 Load and Store Multiple instructions .............................................. A6-18 A6.7 Exception-generating instructions .................................................. A6-20 A6.8 Undefined Instruction space .......................................................... A6-21 Chapter A4 Chapter A5 Chapter A6 vi Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I Chapter A7 Part B Chapter B1 Thumb Instructions A7.1 Alphabetical list of Thumb instructions ............................................. A7-2 A7.2 Thumb instructions and architecture versions .............................. A7-125 Memory and System Architectures Introduction to Memory and System Architectures B1.1 About the memory system ............................................................... B1-2 B1.2 Memory hierarchy ............................................................................ B1-4 B1.3 L1 cache .......................................................................................... B1-6 B1.4 L2 cache .......................................................................................... B1-7 B1.5 Write buffers ..................................................................................... B1-8 B1.6 Tightly Coupled Memory .................................................................. B1-9 B1.7 Asynchronous exceptions .............................................................. B1-10 B1.8 Semaphores ................................................................................... B1-12 Memory Order Model B2.1 About the memory order model ........................................................ B2-2 B2.2 Read and write definitions ................................................................ B2-4 B2.3 Memory attributes prior to ARMv6 ................................................... B2-7 B2.4 ARMv6 memory attributes - introduction .......................................... B2-8 B2.5 Ordering requirements for memory accesses ................................ B2-16 B2.6 Memory barriers ............................................................................. B2-18 B2.7 Memory coherency and access issues .......................................... B2-20 The System Control Coprocessor B3.1 About the System Control coprocessor ............................................ B3-2 B3.2 Registers .......................................................................................... B3-3 B3.3 Register 0: ID codes ........................................................................ B3-7 B3.4 Register 1: Control registers .......................................................... B3-12 B3.5 Registers 2 to 15 ............................................................................ B3-18 Virtual Memory System Architecture B4.1 About the VMSA .............................................................................. B4-2 B4.2 Memory access sequence ............................................................... B4-4 B4.3 Memory access control .................................................................... B4-8 B4.4 Memory region attributes ............................................................... B4-11 B4.5 Aborts ............................................................................................. B4-14 B4.6 Fault Address and Fault Status registers ....................................... B4-19 B4.7 Hardware page table translation .................................................... B4-23 B4.8 Fine page tables and support of tiny pages ................................... B4-35 B4.9 CP15 registers ............................................................................... B4-39 Protected Memory System Architecture B5.1 About the PMSA .............................................................................. B5-2 Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. vii Chapter B2 Chapter B3 Chapter B4 Chapter B5 ARM DDI 0100I Contents  Contents Chapter B6 Chapter B7 Chapter B8 Part C Chapter C1 Chapter C2 B5.2 Memory access sequence ............................................................... B5-4 B5.3 Memory access control .................................................................... B5-8 B5.4 Memory access attributes .............................................................. B5-10 B5.5 Memory aborts (PMSAv6) .............................................................. B5-13 B5.6 Fault Status and Fault Address register support ............................ B5-16 B5.7 CP15 registers ............................................................................... B5-18 Caches and Write Buffers B6.1 About caches and write buffers ........................................................ B6-2 B6.2 Cache organization .......................................................................... B6-4 B6.3 Types of cache ................................................................................. B6-7 B6.4 L1 cache ........................................................................................ B6-10 B6.5 Considerations for additional levels of cache ................................. B6-12 B6.6 CP15 registers ............................................................................... B6-13 Tightly Coupled Memory B7.1 About TCM ....................................................................................... B7-2 B7.2 TCM configuration and control ......................................................... B7-3 B7.3 Accesses to TCM and cache ........................................................... B7-7 B7.4 Level 1 (L1) DMA model .................................................................. B7-8 B7.5 L1 DMA control using CP15 Register 11 ......................................... B7-9 Fast Context Switch Extension B8.1 About the FCSE ............................................................................... B8-2 B8.2 Modified virtual addresses ............................................................... B8-3 B8.3 Enabling the FCSE .......................................................................... B8-5 B8.4 Debug and Trace ............................................................................. B8-6 B8.5 CP15 registers ................................................................................. B8-7 Vector Floating-point Architecture Introduction to the Vector Floating-point Architecture C1.1 About the Vector Floating-point architecture .................................... C1-2 C1.2 Overview of the VFP architecture .................................................... C1-4 C1.3 Compliance with the IEEE 754 standard ......................................... C1-9 C1.4 IEEE 754 implementation choices ................................................. C1-10 VFP Programmer’s Model C2.1 Floating-point formats ...................................................................... C2-2 C2.2 Rounding .......................................................................................... C2-9 C2.3 Floating-point exceptions ............................................................... C2-10 C2.4 Flush-to-zero mode ........................................................................ C2-14 C2.5 Default NaN mode ......................................................................... C2-16 C2.6 Floating-point general-purpose registers ....................................... C2-17 C2.7 System registers ............................................................................ C2-21 viii Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I Chapter C3 Chapter C4 Chapter C5 Part D Chapter D1 Chapter D2 Chapter D3 C2.8 Reset behavior and initialization .................................................... C2-29 VFP Instruction Set Overview C3.1 Data-processing instructions ............................................................ C3-2 C3.2 Load and Store instructions ........................................................... C3-14 C3.3 Single register transfer instructions ................................................ C3-18 C3.4 Two-register transfer instructions ................................................... C3-22 VFP Instructions C4.1 Alphabetical list of VFP instructions ................................................. C4-2 VFP Addressing Modes C5.1 Addressing Mode 1 - Single-precision vectors (non-monadic) ......... C5-2 C5.2 Addressing Mode 2 - Double-precision vectors (non-monadic) ....... C5-8 C5.3 Addressing Mode 3 - Single-precision vectors (monadic) .............. C5-14 C5.4 Addressing Mode 4 - Double-precision vectors (monadic) ............ C5-18 C5.5 Addressing Mode 5 - VFP load/store multiple ................................ C5-22 Debug Architecture Introduction to the Debug Architecture D1.1 Introduction ...................................................................................... D1-2 D1.2 Trace ................................................................................................ D1-4 D1.3 Debug and ARMv6 ........................................................................... D1-5 Debug Events and Exceptions D2.1 Introduction ...................................................................................... D2-2 D2.2 Monitor debug-mode ........................................................................ D2-5 D2.3 Halting debug-mode ......................................................................... D2-8 D2.4 External Debug Interface ............................................................... D2-13 Coprocessor 14, the Debug Coprocessor D3.1 Coprocessor 14 debug registers ...................................................... D3-2 D3.2 Coprocessor 14 debug instructions .................................................. D3-5 D3.3 Debug register reference ................................................................. D3-8 D3.4 Reset values of the CP14 debug registers ..................................... D3-24 D3.5 Access to CP14 debug registers from the external debug interface ......... D3-25 Glossary ............................................... xviii Conventions ........................................................................................ xxi Further reading .................................................................................. xxiii Feedback .......................................................................................... xxiv CPU Architecture Introduction to the ARM Architecture A1.1 About the ARM architecture ............................................................. A1-2 A1.2 ARM instruction set .......................................................................... A1-6 A1.3 Thumb instruction set ..................................................................... A1-11 Programmers’ Model A2.1 Data types ........................................................................................ A2-2 A2.2 Processor modes ............................................................................. A2-3 A2.3 Registers .......................................................................................... A2-4 A2.4 General-purpose registers ............................................................... A2-6 A2.5 Program status registers ................................................................ A2-11 ARM DDI 0100I Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. v Contents Chapter A3 A2.6 Exceptions ..................................................................................... A2-16 A2.7 Endian support ............................................................................... A2-30 A2.8 Unaligned access support .............................................................. A2-38 A2.9 Synchronization primitives ............................................................. A2-44 A2.10 The Jazelle Extension .................................................................... A2-53 A2.11 Saturated integer arithmetic ........................................................... A2-69 The ARM Instruction Set A3.1 Instruction set encoding ................................................................... A3-2 A3.2 The condition field ............................................................................ A3-3 A3.3 Branch instructions .......................................................................... A3-5 A3.4 Data-processing instructions ............................................................ A3-7 A3.5 Multiply instructions ........................................................................ A3-10 A3.6 Parallel addition and subtraction instructions ................................. A3-14 A3.7 Extend instructions ......................................................................... A3-16 A3.8 Miscellaneous arithmetic instructions ............................................ A3-17 A3.9 Other miscellaneous instructions ................................................... A3-18 A3.10 Status register access instructions ................................................ A3-19 A3.11 Load and store instructions ............................................................ A3-21 A3.12 Load and Store Multiple instructions .............................................. A3-26 A3.13 Semaphore instructions ................................................................. A3-28 A3.14 Exception-generating instructions .................................................. A3-29 A3.15 Coprocessor instructions ............................................................... A3-30 A3.16 Extending the instruction set .......................................................... A3-32 ARM Instructions A4.1 Alphabetical list of ARM instructions ................................................ A4-2 A4.2 ARM instructions and architecture versions ................................. A4-286 ARM Addressing Modes A5.1 Addressing Mode 1 - Data-processing operands ............................. A5-2 A5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte ...... A5-18 A5.3 Addressing Mode 3 - Miscellaneous Loads and Stores ................. A5-33 A5.4 Addressing Mode 4 - Load and Store Multiple ............................... A5-41 A5.5 Addressing Mode 5 - Load and Store Coprocessor ....................... A5-49 The Thumb Instruction Set A6.1 About the Thumb instruction set ...................................................... A6-2 A6.2 Instruction set encoding ................................................................... A6-4 A6.3 Branch instructions .......................................................................... A6-6 A6.4 Data-processing instructions ............................................................ A6-8 A6.5 Load and Store Register instructions ............................................. A6-15 A6.6 Load and Store Multiple instructions .............................................. A6-18 A6.7 Exception-generating instructions .................................................. A6-20 A6.8 Undefined Instruction space .......................................................... A6-21 Chapter A4 Chapter A5 Chapter A6 vi Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I Chapter A7 Part B Chapter B1 Thumb Instructions A7.1 Alphabetical list of Thumb instructions ............................................. A7-2 A7.2 Thumb instructions and architecture versions .............................. A7-125 Memory and System Architectures Introduction to Memory and System Architectures B1.1 About the memory system ............................................................... B1-2 B1.2 Memory hierarchy ............................................................................ B1-4 B1.3 L1 cache .......................................................................................... B1-6 B1.4 L2 cache .......................................................................................... B1-7 B1.5 Write buffers ..................................................................................... B1-8 B1.6 Tightly Coupled Memory .................................................................. B1-9 B1.7 Asynchronous exceptions .............................................................. B1-10 B1.8 Semaphores ................................................................................... B1-12 Memory Order Model B2.1 About the memory order model ........................................................ B2-2 B2.2 Read and write definitions ................................................................ B2-4 B2.3 Memory attributes prior to ARMv6 ................................................... B2-7 B2.4 ARMv6 memory attributes - introduction .......................................... B2-8 B2.5 Ordering requirements for memory accesses ................................ B2-16 B2.6 Memory barriers ............................................................................. B2-18 B2.7 Memory coherency and access issues .......................................... B2-20 The System Control Coprocessor B3.1 About the System Control coprocessor ............................................ B3-2 B3.2 Registers .......................................................................................... B3-3 B3.3 Register 0: ID codes ........................................................................ B3-7 B3.4 Register 1: Control registers .......................................................... B3-12 B3.5 Registers 2 to 15 ............................................................................ B3-18 Virtual Memory System Architecture B4.1 About the VMSA .............................................................................. B4-2 B4.2 Memory access sequence ............................................................... B4-4 B4.3 Memory access control .................................................................... B4-8 B4.4 Memory region attributes ............................................................... B4-11 B4.5 Aborts ............................................................................................. B4-14 B4.6 Fault Address and Fault Status registers ....................................... B4-19 B4.7 Hardware page table translation .................................................... B4-23 B4.8 Fine page tables and support of tiny pages ................................... B4-35 B4.9 CP15 registers ............................................................................... B4-39 Protected Memory System Architecture B5.1 About the PMSA .............................................................................. B5-2 Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. vii Chapter B2 Chapter B3 Chapter B4 Chapter B5 ARM DDI 0100I Contents  Contents Chapter B6 Chapter B7 Chapter B8 Part C Chapter C1 Chapter C2 B5.2 Memory access sequence ............................................................... B5-4 B5.3 Memory access control .................................................................... B5-8 B5.4 Memory access attributes .............................................................. B5-10 B5.5 Memory aborts (PMSAv6) .............................................................. B5-13 B5.6 Fault Status and Fault Address register support ............................ B5-16 B5.7 CP15 registers ............................................................................... B5-18 Caches and Write Buffers B6.1 About caches and write buffers ........................................................ B6-2 B6.2 Cache organization .......................................................................... B6-4 B6.3 Types of cache ................................................................................. B6-7 B6.4 L1 cache ........................................................................................ B6-10 B6.5 Considerations for additional levels of cache ................................. B6-12 B6.6 CP15 registers ............................................................................... B6-13 Tightly Coupled Memory B7.1 About TCM ....................................................................................... B7-2 B7.2 TCM configuration and control ......................................................... B7-3 B7.3 Accesses to TCM and cache ........................................................... B7-7 B7.4 Level 1 (L1) DMA model .................................................................. B7-8 B7.5 L1 DMA control using CP15 Register 11 ......................................... B7-9 Fast Context Switch Extension B8.1 About the FCSE ............................................................................... B8-2 B8.2 Modified virtual addresses ............................................................... B8-3 B8.3 Enabling the FCSE .......................................................................... B8-5 B8.4 Debug and Trace ............................................................................. B8-6 B8.5 CP15 registers ................................................................................. B8-7 Vector Floating-point Architecture Introduction to the Vector Floating-point Architecture C1.1 About the Vector Floating-point architecture .................................... C1-2 C1.2 Overview of the VFP architecture .................................................... C1-4 C1.3 Compliance with the IEEE 754 standard ......................................... C1-9 C1.4 IEEE 754 implementation choices ................................................. C1-10 VFP Programmer’s Model C2.1 Floating-point formats ...................................................................... C2-2 C2.2 Rounding .......................................................................................... C2-9 C2.3 Floating-point exceptions ............................................................... C2-10 C2.4 Flush-to-zero mode ........................................................................ C2-14 C2.5 Default NaN mode ......................................................................... C2-16 C2.6 Floating-point general-purpose registers ....................................... C2-17 C2.7 System registers ............................................................................ C2-21 viii Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I Chapter C3 Chapter C4 Chapter C5 Part D Chapter D1 Chapter D2 Chapter D3 C2.8 Reset behavior and initialization .................................................... C2-29 VFP Instruction Set Overview C3.1 Data-processing instructions ............................................................ C3-2 C3.2 Load and Store instructions ........................................................... C3-14 C3.3 Single register transfer instructions ................................................ C3-18 C3.4 Two-register transfer instructions ................................................... C3-22 VFP Instructions C4.1 Alphabetical list of VFP instructions ................................................. C4-2 VFP Addressing Modes C5.1 Addressing Mode 1 - Single-precision vectors (non-monadic) ......... C5-2 C5.2 Addressing Mode 2 - Double-precision vectors (non-monadic) ....... C5-8 C5.3 Addressing Mode 3 - Single-precision vectors (monadic) .............. C5-14 C5.4 Addressing Mode 4 - Double-precision vectors (monadic) ............ C5-18 C5.5 Addressing Mode 5 - VFP load/store multiple ................................ C5-22 Debug Architecture Introduction to the Debug Architecture D1.1 Introduction ...................................................................................... D1-2 D1.2 Trace ................................................................................................ D1-4 D1.3 Debug and ARMv6 ........................................................................... D1-5 Debug Events and Exceptions D2.1 Introduction ...................................................................................... D2-2 D2.2 Monitor debug-mode ........................................................................ D2-5 D2.3 Halting debug-mode ......................................................................... D2-8 D2.4 External Debug Interface ............................................................... D2-13 Coprocessor 14, the Debug Coprocessor D3.1 Coprocessor 14 debug registers ...................................................... D3-2 D3.2 Coprocessor 14 debug instructions .................................................. D3-5 D3.3 Debug register reference ................................................................. D3-8 D3.4 Reset values of the CP14 debug registers ..................................... D3-24 D3.5 Access to CP14 debug registers from the external debug interface ......... D3-25 Glossary