基于VHDL的加法器的设计

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER10B IS PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END ADDER10B; ARCHITECTURE behav OF ADDER10B IS